IP Library Granted Patent US 8,197,638
Granted Patent B2
US 8,197,638 · App. 10/589,490 · Granted Jun 12, 2012

Semiconductor manufacturing device and method for manufacturing semiconductor devices

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Quick Facts
Patent No.
US 8,197,638
App. No.
10/589,490
Granted
Jun 12, 2012
Kind
B2
Abstract

Wafer contamination is prevented, while preventing damage to a high-frequency electrode and a susceptor. A main body 41 of the susceptor 40 of an MMT apparatus is composed of a heater arranging plate 42 , an electrode arranging plate 48 , and a supporting plate 56 all made from quartz. A circular electrode arranging hole 49 with a fixed depth is concentrically formed on the upper surface of the electrode arranging plate 48 , and quadrangular pillars 50 are formed protruding in a matrix on the bottom of the electrode arranging hole 49 . Multiple insertion holes 52 are formed in a disk-shaped high-frequency electrode 51 , and the high-frequency electrode 51 is installed in the electrode arranging hole 49 by inserting each pillar 50 into each insertion hole 52 . The gaps Sa and Sb are provided between the high-frequency electrode 51 and the electrode arranging plate 48 . The pillar 50 boosts the strength of the electrode arranging plate 48 . Damage to the high-frequency electrode is prevented even if the thermal expansion coefficient of the high-frequency electrode is larger than that of the electrode arranging plate, since the gaps absorb the thermal expansion differential.

Claims (8)

1. A semiconductor manufacturing device comprising a processing chamber including a susceptor for supporting a substrate, wherein the susceptor has a main body containing a wall forming inside an electrode arranging space substantially flat and parallel to the substrate and multiple pillars joining the bottom and ceiling of the wall; and a high-frequency electrode having at least one insertion hole for receiving at least one of the multiple pillars, the high-frequency electrode being installed with a gap between the electrode and the at least one of the multiple pillars within the electrode arranging space.

2. A semiconductor manufacturing device according to claim 1 , wherein the distance from the high frequency electrode to the supporting surface for supporting the substrate provided on the susceptor surface higher than the high-frequency electrode, is set smaller than the distance from the high-frequency electrode to the susceptor rear surface lower than the high-frequency electrode.

3. A semiconductor manufacturing device according to claim 1 or claim 2 , wherein the electrode arranging space is insulated from the atmosphere in the processing chamber and is connected to the atmosphere outside the processing chamber.

4. A semiconductor manufacturing device according to claim 1 or claim 2 , wherein the high-frequency electrode is comprised of a plate formed with insertion holes where the pillars are inserted.

5. A method for manufacturing semiconductor devices comprising the steps of:

supporting a substrate on a susceptor installed in a processing chamber,

supplying and exhausting a process gas to and from the processing chamber, and

performing plasma processing of the substrate by the susceptor having a main body containing a wall forming inside an electrode arranging space substantially flat and parallel to the substrate and multiple pillars joining the bottom and ceiling of the wall; and a high-frequency electrode having at least one insertion hole for receiving at least one of the multiple pillars, the high-frequency electrode being installed with a gap between the electrode and the at least one of the multiple pillars within the electrode arranging space.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 31, 2018
From: HITACHI KOKUSAI ELECTRIC INC.
To: KOKUSAI ELECTRIC CORPORATION
Reel/Frame 048008/0206 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 22, 2007
From: ISHISAKA, MITSUNORI; MIYATA, TOSHIMITSU
To: HITACHI KOKUSAI ELECTRIC INC.
Reel/Frame 019327/0270 →