Granted Patent B2

US 7,394,144 · App. 10/594,487 · Granted Jul 1, 2008

Abstract

Claims (39)

1. A method of manufacturing a semiconductor device, comprising:

(a) providing a silicon semiconductor body having opposed first and second major surfaces having a lower-doped region at the first major surface above a higher doped region, the lower-doped region and the higher doped region both being doped to have a first conductivity type, the lower-doped region having a lower doping than the higher doped region;

(b) defining a mask having openings on the first major surface;

(c) forming trenches through the openings in the mask, the trenches extending from the first major surface towards the second major surface through the lower-doped region towards the higher doped region;

(d) depositing a trench insulating layer on the sidewalls and base of the trenches as well as the first major surface;

(e) removing the trench insulating layer from the top of the sidewalls of the trenches adjacent to the first major surface leaving exposed silicon at the top of the sidewalls of the trench; and

(f) growing silicon selectively on the exposed silicon to grow silicon at the top of the trenches and plugging the top of the trenches,

wherein the method further includes defining a structure for depleting the lower-doped region in an operating state of the semiconductor device to allow the lower-doped region to support a voltage in that operating state.

2. The method as recited in claim 1 further comprising the step of doping the sidewalls of the trenches to have a second conductivity type opposite to the first conductivity type to form the structure for depleting the lower-doped region before depositing the trench insulating layer.

3. The method as recited in claim 1 further comprising:

(g) forming a body region ( 22 ) being semiconductor doped to be of second conductivity type opposite to the first conductivity type at or adjacent to the first major surface ( 80 ) and adjacent to the trenches ( 8 ).

4. The method as recited in claim 3 further comprising the steps:

(h) forming a source region of semiconductor doped to be of the first conductivity type at or adjacent to the first major surface and in contact with the body region; and

(i) forming an insulated gate for controlling conduction between source region and higher doped region acting as the drain through the body.

5. The method as recited in claim 1 wherein

step (e) comprises overetching to remove the trench insulating layer from the base of the trenches and the first major surface as well as the top of the sidewalls of the trenches adjacent to the first major surface leaving the exposed silicon at the top of the sidewalls of the trench and the base of the trenches.

6. The method as recited in claim 1 further comprising the step of depositing semi-insulating polysilicon on the sidewalls of the trenches to form the structure for depleting the lower-doped region.

7. The method as recited in claim 6 further comprising the steps, after step (c), of:

depositing an outer trench insulating layer on the sidewalls of the trench and the top surface;

removing the outer trench insulating layer from the base of the trench;

followed by the steps of depositing semi-insulating polysilicon in the trench and then step (d) of depositing a trench insulating layer;

wherein step (e) of overetching includes one or more etching steps etching the outer insulating layer, the semi-insulating polysilicon and the trench insulating layer to expose the sidewalls of the trenches adjacent to the first major surface.

8. The method as recited in claim 1 wherein in step (f):

silicon is grown selectively on the exposed sidewalls at the top of the trench leaving a gap between the silicon ( 70 ) grown on opposed sidewalls;

a silicon layer is deposited on the first major surface plugging the gap in the trench;

and the silicon layer deposited on the first major surface is removed, leaving the silicon layer plugging the gap.

9. A semiconductor device, comprising:

a silicon semiconductor body having opposed first and second major surfaces having a lower-doped region above a higher-doped region, the lower-doped region and the higher-doped region both being doped to have a first conductivity type;

trenches extending from the first major surface towards the second major surface through the lower-doped region towards the higher doped region;

a silicon plug plugging the top of the trenches above a void in the trenches; and

a structure for depleting the lower-doped region in an operating state of the semiconductor device to allow the lower-doped region to support a voltage in that operating state.

10. A semiconductor device according to claim 9 wherein the semiconductor adjacent to the sidewalls of the trenches is doped to be of a second conductivity type forming the structure for depleting the lower-doped region.

11. The semiconductor device as recited in claim 9 further comprising a layer of semi-insulating polysilicon extending along the sidewalls of the trenches forming the structure for depleting the lower-doped region, the semi-insulating polysilicon being in electrical connection with the semiconductor under the trench and to the silicon plug at the top of the trench.

12. The semiconductor device according to claim 9 , having an active region and an edge termination region around the active region, wherein a plurality of the trenches form an edge termination structure in the edge termination region, edge body regions doped to be of second conductivity type opposite to the first conductivity type extend between the trenches in the edge termination region, and the silicon plugs in the trenches in the edge termination region are undoped to form a high-resistance path between the edge body regions on either side of the trenches.

13. A semiconductor device according to claim 12 comprising a plurality of the trenches plugged with a silicon plug in the active region, the silicon plugs in the trenches in the active region being doped to be conductive.

14. The semiconductor device according to claim 9 further comprising:

a body region being semiconductor doped to be of second conductivity type at or adjacent to the first major surface and adjacent to the trenches; and

a source region of semiconductor doped to be of the first conductivity type at or adjacent to the first major surface and in contact with the body region; and

an insulated gate for controlling conduction through the body region between the source region and the higher-doped region acting as a drain.

Assignments (13)