IP Library Granted Patent US 6,937,069
Granted Patent B2
US 6,937,069 · App. 10/601,993 · Granted Aug 30, 2005

System and method for dead-band determination for rotational frequency detectors

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Quick Facts
Patent No.
US 6,937,069
App. No.
10/601,993
Granted
Aug 30, 2005
Kind
B2
Abstract

In one embodiment a system and method is arranged for bridging the dead-band when asynchronous signals are compared against each other. There is developed a pair of phase related signals from one of the signals, each phase related signal phase shifted from each other, but having the same frequency as the signal from which it was derived. The other frequency signal is compared against each of the phase-related developed signals to generate an error signal which quadrature rotates when the first and second signals are out of frequency with each other. A control signal is generated when the quadrature rotation is outside a certain limit. The error signal is controllably buffered to insure that the error signal only occurs when the frequencies are offset for a selected period of time.

Claims (54)

1. A method for bridging dead-band when a signal having a first frequency is compared against a signal having a second frequency, said method comprising:

developing from said second frequency signal a pair of phase related signals each of said phase related signals having the same frequency but phase shifted from each other, said same frequency being controlled by said second frequency signal;

comparing said first signal against each of said phase related signals to generate a quadrature vector that rotates when said first and second frequency signals differ in frequency from each other; and

resolving a metastability by allowing a portion of a rotation of the quadrature vector before asserting an output signal.

2. The method of claim 1 wherein said method further comprises:

generating a control signal when said quadrature rotation is outside a certain limit.

3. The method of claim 2 wherein said certain limit is controllable.

4. The method of claim 2 wherein said certain limit is different for different quadrature rotation directions.

5. The method of claim 2 wherein said comparing comprises:

generating the output signal based on a mismatch between said first frequency signal and each of said generated phase-shifted signals;

deriving a frequency divided signal from said first frequency signal; and

clocking said output signal against said frequency divided signal.

6. The method of claim 5 further comprising:

adjusting said frequency divided signal to control said certain limit.

7. A system for bridging dead-band when a first signal having a first frequency is compared against a second signal having a second frequency, said system comprising:

circuitry for developing from one of said signals a pair of phase related signals each said phase related signal having the same frequency as said signal from which said phase related signals developed;

comparing circuitry for comparing the other of said signals against each of said phase related signals to generate a quadrature vector that rotates when said first and second signals differ in frequency from each other; and

circuitry for allowing a portion of a rotation of the quadrature vector before asserting an output signal to resolve a metastability.

8. The system of claim 7 further comprising:

generating circuitry for generating a control signal when said quadrature rotation is outside a certain limit.

9. The system of claim 8 wherein said certain limit is controllable.

10. The system of claim 8 wherein said certain limit is different for different quadrature rotation directions.

11. The system of claim 8 wherein said comparing circuitry comprises:

circuitry for generating the output signal based on a mismatch between said other of said signals and each of said generated phase-shifted signals;

circuitry for deriving a frequency divided signal from said other of said signals; and

circuitry for clocking said output signal against said frequency divided signal.

12. The system of claim 11 further comprising:

circuitry for adjusting said frequency divided signal to control said certain limit.

13. A circuit for comparing two asynchronous signals, said circuit comprising:

a phase detector;

a frequency detector for detecting both the magnitude and polarity of any frequency difference between said signals, said frequency detector yielding control of said circuit to said phase detector when the frequency difference is within a dead-band region; and

circuitry for delaying a glitch within said dead-band region for a period of time to allow the glitch to resolve.

14. The circuit of claim 13 further comprising:

circuitry for developing from a first one of said signals a pair of phase related signals each said phase related signal having the same frequency as first one of said signals but phase shifted 90 degrees therefrom; and

circuitry for comparing a second one of said signals against each of said phase-related signals to generate a quadrature rotating error signal when said compared signals differ in frequency from each other.

15. The circuit of claim 14 wherein said comparing circuitry comprises:

circuitry for generating output signals based on mismatches between the second one of said signals and each of said generated phase-shifted signals;

circuitry for deriving a frequency divided signal from said first one of said signals; and

circuitry for clocking said output signals against said frequency divided signal.

16. The circuit of claim 15 further comprising:

circuitry for adjusting a frequency divided signal to control a certain limit.

17. A method for comparing two asynchronous signals, said method comprising the steps of:

comparing the phase of said signals;

comparing both the magnitude and polarity of any frequency difference between said signals to yield control to said phase comparison when the frequency difference is within a dead-band region;

generating quadrature signals from one of said compared signals;

comparing the other of said signals against said quadrature signals to yield a signal which has a speed of rotation having a relationship to any mismatch between said signals, and

delaying a glitch within said dead-band region for a period of time to allow the glitch to resolve said delaying a function of said speed of said phase rotation.

18. A VCO circuit having a VCO output voltage and a reference voltage, said circuit comprising:

a phase detector;

a frequency detector for detecting both the magnitude and polarity of any frequency difference between said reference signal and said VCO output voltage, said frequency detector yielding control of said circuit to said phase detector when the frequency difference is within a dead-band region; and

circuitry for delaying a glitch within said dead-band region for a period of time to allow the glitch to resolve.

19. The VCO circuit of claim 18 further comprising:

circuitry for developing from said VCO output voltage a pair of phase related signals each said phase related signal having the same frequency as said VCO output voltage but phase shifted 90 degrees therefrom; and

circuitry for comparing said reference signal against each of said developed signals to generate a quadrature rotating an error signal when said reference signal and said VCO output voltage are out of frequency with each other.

Assignments (9)
MERGER Recorded Mar 3, 2023
From: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED; BROADCOM INTERNATIONAL PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 062952/0850 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 14, 2020
From: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
To: BROADCOM INTERNATIONAL PTE. LTD.
Reel/Frame 053771/0901 →
CORRECTIVE ASSIGNMENT TO CORRECT THE EXECUTION DATE PREVIOUSLY RECORDED AT REEL: 047196 FRAME: 0097. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Mar 6, 2019
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 048555/0510 →
MERGER Recorded Oct 4, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047196/0097 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NAME OF THE ASSIGNEE PREVIOUSLY RECORDED ON REEL 017207 FRAME 0020. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded May 6, 2016
From: AGILENT TECHNOLOGIES, INC.
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 038633/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032851-0001) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 037689/0001 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032851/0001 →