Sonos multi-level memory cell
View Patent ↗A multi-level memory cell includes a substrate, an insulation layer, a silicon stripe, a first control gate, a second control gate, source/drain regions, silicon oxide/silicon nitride/silicon oxide composite layers. The insulation layer and the silicon stripe are sequentially disposed on the substrate. The first control gate and the second control gate are respectively disposed on the sidewalls of the silicon stripe, while the source/drain regions are configured in the silicon stripe beside both sides of the first control gate and the second control gate. The composite dielectric layers are disposed between the first control gate and the silicon stripe, and between the second control gate and the silicon stripe. Since a single memory structure can store a multiple bit of information, it is advantageous for minimizing devices.
1. A multi-level SONOS memory cell, comprising:
a substrate, comprising:
a substrate layer;
an insulation layer, disposed on the substrate layer;
a silicon stripe, disposed on the insulation layer;
a first control gate and a second control gate disposed respectively and separately on sidewalls of the silicon stripe;
source/drain regions, configured in the silicon stripe beside both sides of the first control gate and the second control gate; and
a silicon oxide/silicon nitride/silicon oxide composite layer, disposed between the first control gate and the silicon stripe, and between the second control gate and the silicon stripe.
2. The memory cell of claim 1 , wherein the substrate comprises a silicon-on-insulator substrate.
3. A multi-level memory cell, comprising:
a substrate;
an insulation layer, disposed on the substrate;
a semiconductive stripe, disposed on the insulation layer;
a first control gate and a second control gate disposed respectively and separately on sidewalls of the semiconductive stripe;
source/drain regions, configured in the semiconductive stripe beside both sides of the first conductive gate and the second conductive gate;
a charge trapping layer, disposed between the first control gate and the semiconductive stripe, and between the second control gate and the semiconductive stripe;
a first dielectric layer, disposed between the charge trapping layer and the semiconductive stripe; and
a second dielectric layer, disposed between the charge trapping layer and the first control gate, and between the charge trapping layer and the second control gate.
4. The multi-level memory cell of claim 3 , wherein the semiconductive stripe comprises silicon.
5. The multi-level memory cell of claim 3 , wherein the charge trapping layer comprises a silicon nitride layer.
6. The multi-level memory cell of claim 3 , wherein the first dielectric layer comprises a silicon oxide layer.
7. The multi-level memory cell of claim 3 , wherein the second dielectric layer comprises a silicon oxide layer.