Flash memory cell, flash memory cell array and manufacturing method thereof
View Patent ↗A flash memory cell array comprises a substrate, a string of memory cell structures and source region/drain region. Each of memory cell structures includes a stack gate structure including a select gate dielectric layer, a select gate and a gate cap layer formed on the substrate; a spacer is set on the sidewall of the select gate; a control gate connected to the stack gate structure is set on the one side of the stack gate structure; a floating gate is set between the control gate and the substrate; an inter-gate dielectric layer is set between the control gate and the floating gate; and a tunneling dielectric layer is set between the floating gate and the substrate. The source region/drain region is set in the substrate near outer control gate and stack gate structure of the flash memory cell array.
1. A flash memory cell, comprising:
a substrate;
a stack gate structure formed on said substrate, said stack gate structure including a select gate dielectric layer, a select gate, and a gate cap layer, said select gate dielectric layer being formed between said substrate and said select gate, said gate cap layer being formed on said select gate;
a spacer formed along a sidewall of said select gate;
a control gate formed on one side of said stack gate structure and connected to said stack gate structure;
a floating gate formed between said control gate and said substrate and including a recess, wherein a top surface of said floating gate layer is positioned between a top surface of said spacer and a top surface of said gate cap layer;
an inter-gate dielectric layer formed between said control gate and said floating gate;
a tunneling dielectric layer formed between said floating gate and said substrate; and
a drain region and a source region formed in said substrate, wherein said drain region and said source region formed on the one side and the other side of said control gate and said stack gate structure respectively.
2. The flash memory cell of claim 1 , wherein said inter-gate dielectric layer comprises silicon dioxide/silicon nitride/silicon dioxide.
3. A flash memory cell array, comprising:
a substrate;
a plurality of flash memory cell structures formed on said substrate, wherein each of said flash memory cell structures including
a stack gate structure formed on said substrate and including a select gate dielectric layer, a select gate, and a gate cap layer, wherein said select gate dielectric layer is formed between said substrate and said select gate, and said gate cap layer is formed on said select gate;
a spacer formed along a sidewall of said select gate;
a control gate formed on the one side of said stack gate structure and connected to said stack gate structure;
a floating gate formed between said control gate and said substrate, wherein a top surface of said floating gate layer is positioned between a top surface of said spacer and a top surface of said gate cap layer;
an inter-gate dielectric layer formed between said control gate and said floating gate, wherein said control gate and said floating gate constitute a stack structure;
a tunneling dielectric layer formed between said floating gate and said substrate; and
a drain region and a source region formed in said substrate, said drain region and said source region formed on the one side and the other side of said control gate and said stack gate structure respectively;
wherein said stack gate structure juxtaposes alternatively with said stack structure in said flash memory cell structures.
4. The flash memory cell array of claim 3 , wherein said floating gate includes a recess, and said recess is substantially filled with said control gate.
5. The flash memory cell array of claim 3 , wherein said inter-gate dielectric layer comprises silicon dioxide/silicon nitride/silicon dioxide.