Integrated circuit and method for interfacing two voltage domains using a transformer
View Patent ↗An integrated circuit designed to reduce on-chip noise coupling. In one embodiment, circuit ( 60 ) includes the following: a circuit transformer ( 62 ) capable of converting a noise sensitive input reference clock signal to an output signal having a voltage compatible with a predetermined sink voltage logic level; and a biased receiver network ( 64 ) having a PFET current mirror ( 74 ) coupled with a NFET current ( 72 ), the biased receiver transistor network designed to multiply the transformer signal to offset a mutual coupling loss of the transformer. In at least one alternative embodiment, the input reference clock signal originates at an off-chip clock generator circuit ( 42 ) and the output signal from receiver ( 64 ) is input to a PLL ( 44 ). In another alternative embodiment, the transformer is a monolithic integrated transformer. Another alternative embodiment of the present invention is a method of reducing on-chip noise coupling.
1. An integrated circuit designed to reduce on-chip noise coupling, the integrated circuit comprising:
a circuit transformer capable of converting a noise sensitive input signal to an output signal having a voltage compatible with a predetermined sink voltage logic level; and
a biased receiver transistor network having a PFET current mirror coupled with a NFET current mirror, said biased receiver transistor network designed to multiply said transformer output signal to offset a mutual coupling loss of said transformer.
2. An integrated circuit according to claim 1 , wherein said input signal originates in a first voltage domain and said output signal from said biased receiver transistor network is output to a second voltage domain, said second voltage domain being noncontiguous with said first voltage domain.
3. An integrated circuit according to claim 1 , wherein said input signal originates at an off-chip signal source and is output to an on-chip signal sink included in on-chip analog circuitry.
4. An integrated circuit according to claim 3 , wherein said off-chip signal source is a reference clock.
5. An integrated circuit according to claim 1 , wherein said output signal from said biased receiver transistor network is input to a PLL.
6. An integrated circuit according to claim 1 , wherein said transformer is a monolithic integrated transformer.
7. A method of reducing electrical noise coupling to a noise-sensitive chip input signal, comprising the steps of:
providing input circuitry including a noise isolated monolithic integrated transformer;
converting a noise-sensitive chip input signal to an intermediate signal using said transformer;
converting said intermediate signal to a converted signal having a voltage level compatible with that of a predetermined logic level using auxiliary noise-isolated support circuitry; and
using said converted signal as input to intended on-chip destination circuitry.
8. A method according to claim 7 , wherein said step of converting the transformed signal is performed using a biased receiver transistor network having a PFET current mirror coupled with a NFET current mirror.
9. A method according to claim 7 , wherein said input signal in said step of converting a noise-sensitive chip input signal originates at an off-chip signal source and is output to an on-chip signal sink included in on-chip analog circuitry.
10. A method according to claim 9 , wherein said off-chip signal source is a reference clock.
11. The method according to claim 7 , further comprising the step of:
multiplying said transformer output signal to offset a mutual coupling loss of said transformer.
12. A method according to claim 11 , wherein said converted signal in said multiplying step is input to a PLL.
13. An integrated circuit designed to reduce on-chip noise coupling, the integrated circuit comprising:
a monolithic integrated circuit transformer for converting a noise sensitive input signal to an output signal having a voltage compatible with a predetermined sink voltage logic level; and
means for multiplying said transformer output signal to offset a mutual coupling loss of said transformer.
14. An integrated circuit according to claim 13 , wherein said means for multiplying is a biased receiver transistor network having a PFET current mirror coupled with a NFET current mirror.
15. An integrated circuit according to claim 13 , wherein said input signal originates in a first voltage domain and said output signal from said biased receiver transistor network is output to a second voltage domain, said second voltage domain being noncontiguous with said first voltage domain.
16. An integrated circuit according to claim 13 , wherein said input signal from said biased receiver transistor network is input to a PLL.