IP Library Granted Patent US 7,279,355
Granted Patent B2
US 7,279,355 · App. 10/608,606 · Granted Oct 9, 2007

Method for fabricating a packaging device for semiconductor die and semiconductor device incorporating same

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Quick Facts
Patent No.
US 7,279,355
App. No.
10/608,606
Granted
Oct 9, 2007
Kind
B2
Abstract

A substantially planar substrate having opposed major surfaces is provided. The substrate includes a through hole that extends between the major surfaces. The through hole is filled with a conductive interconnecting element. A conductive mounting pad and a conductive connecting pad are formed on different ones of the major surfaces in electrical contact with the conductive interconnecting element. The packaging device formed by the method has a volume that is only a few times that of the semiconductor die and can be fabricated from materials that can withstand high-temperature die attach processes. The packaging device can be configured as the only packaging device used in the semiconductor device or as a submount for a semiconductor die that requires a high-temperature die attach process.

Claims (20)

1. A method for fabricating a device, the method comprising:

providing a substantially planar substrate having opposed major surfaces, the substrate comprising a through hole extending between the major surfaces;

providing a slug of an electrically conductive material;

squeezing the slug into the through hole whereby the slug is retained in the through hole by friction; and

forming an electrically conductive die mounting pad and an electrically conductive connecting pad on different ones of the major surfaces each pad being in electrical contact with the slug.

2. The method of claim 1 , additionally comprising attaching a semiconductor die to the die mounting pad.

3. The method of claim 2 , additionally comprising:

providing a packaging device, the packaging device including a conductive mounting surface; and

mounting the device in the packaging device, the mounting comprising attaching the connecting pad to the conductive mounting surface of the packaging device.

4. The method of claim 2 , in which:

providing a substrate comprises providing a wafer of which the substrate constitutes part; and

the method additionally comprises, after the filling, the forming and the attaching, singulating the wafer into individual devices.

5. The method of claim 4 , additionally comprising performing electrical testing prior to the singulating.

6. The method of claim 4 , additionally comprising performing electro-optical testing prior to the singulating.

7. The method of claim 2 , additionally comprising encapsulating the semiconductor die and at least a portion of the major surfaces of the substrate on which the die mounting pad is located.

8. The method of claim 1 , wherein the slug has a diameter that is smaller than a diameter of the through hole, the smaller diameter selected to provide a friction fit between the slug and the through hole.

9. The method of claim 8 , wherein the ends of the slug are located approximately flush with the opposed major surfaces.

10. The method of claim 1 , wherein the slug comprises tungsten.

11. The method of claim 1 , wherein the slug occupies at least a portion of a volume of the through hole.

12. The method of claim 11 , wherein an adhesive is used to hold the slug in the through hole.

Assignments (6)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 17, 2016
From: INTELLECTUAL DISCOVERY CO. LTD.
To: DOCUMENT SECURITY SYSTEMS, INC.
Reel/Frame 040744/0174 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE NAME PREVIOUSLY RECORDED AT REEL: 017206 FRAME: 0666. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded May 6, 2016
From: AGILENT TECHNOLOGIES, INC.
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 038632/0662 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 17, 2012
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.; AVAGO TECHNOLOGIES ECBU IP (SINGAPORE) PTE. LTD.; AVAGO TECHNOLOGIES FIBER IP (SINGAPORE) PTE. LTD.
To: INTELLECTUAL DISCOVERY CO., LTD.
Reel/Frame 028972/0733 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 25, 2006
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES ECBU IP (SINGAPORE) PTE. LTD.
Reel/Frame 017675/0518 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 22, 2006
From: AGILENT TECHNOLOGIES, INC.
To: AVAGO TECHNOLOGIES GENERAL IP PTE. LTD.
Reel/Frame 017206/0666 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 26, 2003
From: LEE, KONG WENG; NG, KEE YEAN; KUAN, YEW CHEONG; TAN, GIN GHEE; TAN, CHENG WHY
To: AGILENT TECHNOLOGIES, INC.
Reel/Frame 014011/0029 →