Method for manufacturing merged DRAM with logic device
View Patent ↗In manufacturing merged DRAM with a logic device in a single chip, an oxide layer and a nitride layer are formed on a semiconductor substrate. A hole for exposing the substrate is formed. A silicon epitaxial layer is grown on a portion of the substrate exposed by the hole and an adjacent portion of the nitride layer so that a facet is formed on the nitride layer surface. A thermal oxide layer is grown on the silicon epitaxial layer. The thermal oxide layer is wet etched so that only a growing portion is left on the silicon epitaxial layer. The thermal oxide layer left on the facets of the repeatedly grown silicon epitaxial layer is removed. A gate oxide layer and a gate conductive layer are formed on the resulting substrate. A gate is formed by patterning the gate conductive and oxide layer. A capacitor having a storage node, a dielectric layer, and a plate node is also formed.
1. A method for manufacturing a merged DRAM with logic (MDL) device, the method comprising the steps of: a) forming an oxide layer and a nitride layer one by one on a semiconductor substrate; b) forming a hole for exposing the substrate through patterning the nitride layer and the oxide layer; c) growing a silicon epitaxial layer on a portion of the substrate exposed by the hole and an adjacent portion of the nitride layer so that a facet is formed on the surface of the nitride layer; d) growing a thermal oxide layer on the grown silicon epitaxial layer; e) wet etching the thermal oxide layer so that only a growing portion thereof is left on the facet of the silicon epitaxial layer; f) repeating steps of c), d) and e) a predetermined number of times; g) removing the thermal oxide layer left on the facets of the repeatedly grown silicon epitaxial layers; h) serially forming a gate oxide layer and a gate conductive layer on the resulting substrate from step g); and i) forming a gate through patterning the gate conductive layer and the gate oxide layer, and forming a capacitor as well, comprising a storage node consisting of the substrate and the silicon epitaxial layer repeatedly grown as to leave a facet of the silicon epitaxial layer, a dielectric layer consisting of the gate oxide layer, and a plate node consisting of the gate conductive layer.
2. A method for manufacturing an MDL device as claimed in claim 1 , wherein the silicon epitaxial layer is doped with an impurity.
3. A method for manufacturing an MDL device as claimed in claim 2 , wherein the impurity doping is performed in such a manner that, during growing of the silicon epitaxial layer, impurity gas is added.
4. A method for manufacturing an MDL device as claimed in claim 2 , wherein the impurity doping is performed in such a manner that, after growth of the silicon epitaxial layer, ion implantation or POC13 method is carried out.
5. A method for manufacturing an MDL device as claimed in claim 4 , wherein the ion implantation is carried out in such a manner that impurity ions are implanted at an angle between 5 and 60 degrees.