On-chip signal state duration measurement and adjustment
View Patent ↗Signal state durations, such as the pulse-width, of on-chip signals are often critical to the successful operation of an integrated circuit. The signal state durations measured by on-chip technology provide signal state duration information to an on-chip signal state duration control system. The signal state duration control system uses the information to adjust the signal state duration of an on-chip signal. In one embodiment, the signal state duration of the on-chip signal is the pulse width of the on-chip signal. The signal duration measurement and adjustment system is, for example, useful for measuring the state duration of signals such as self-resetting signals, which are difficult to externally measure and adjust signal state durations using on-chip technology.
1. A method of adjusting a signal state duration of an on-chip signal using one or more on-chip systems, the method comprising:
(a) determining the signal state duration of the on-chip signal within a range of accuracy using on-chip circuitry;
(b) comparing the signal state duration of the on-chip signal to a known propagation time of a test data signal using a first on-chip system; and
(c) if the determined signal state duration of the on-chip signal does not have a desired value, adjusting the signal state duration towards the desired value using a second on-chip system.
2. The method of claim 1 wherein the signal state duration of the on-chip signal is the pulse-width of the on-chip signal.
3. The method of claim 1 wherein adjusting the pulse-width of the signal towards the desired value comprises adjusting a rising edge time delay of each of one or more driver stages of the signal.
4. The method of claim 1 wherein adjusting the pulse-width of the signal towards the desired value comprises adjusting a falling edge time delay of each of one or more driver stages of the signal.
5. The method of claim 1 wherein adjusting the pulse-width of the signal towards the desired value comprises adjusting a P/N strength of one or more driver stages of the signal.
6. The method of claim 5 wherein each of the one or more driver stages comprises a first pull-up driver circuit and adjusting the P/N strength of one or more driver stages of the signal comprises:
adjusting a turn-on delay time of one or more of the first pull-up driver circuits using one or more additional pull-up driver circuits coupled in series with one or more of the first pull-up driver circuits.
7. The method of claim 5 wherein each of the one or more driver stages comprises a first pull-down driver circuit and adjusting the P/N strength of one or more driver stages of the signal comprises:
adjusting a turn-on delay time of one or more of the first pull-down driver circuits using one or more additional pull-down driver circuits coupled in series with one or more of the first pull-down driver circuits.
8. The method of claim 5 wherein each of the one or more driver stages comprises a first pull-down driver circuit and a first pull-down driver circuit and adjusting the P/N strength of one or more driver stages of the signal comprises:
adjusting a turn-on delay time of one or more of the first pull-down driver circuits using one or more additional pull-down driver circuits coupled in series with one or more of the first pull-down driver circuits; and
adjusting a turn-on delay time of one or more of the first pull-up driver circuits using one or more additional pull-up driver circuits coupled in series with one or more of the first pull-up driver circuits.
9. The method of claim 5 wherein each of the one or more driver stages comprises a first pull-up driver circuit and adjusting the P/N strength of one or more driver stages of the signal comprises:
adjusting a turn-on delay time of one or more of the first pull-up driver circuits using one or more additional pull-up driver circuits coupled in parallel with one or more of the first pull-up driver circuits.
10. The method of claim 5 wherein each of the one or more driver stages comprises a first pull-down driver circuit and adjusting the P/N strength of one or more driver stages of the signal comprises:
adjusting a turn-on delay time of one or more of the first pull-down driver circuits using one or more additional pull-down driver circuits coupled in parallel with one or more of the first pull-down driver circuits.
11. The method of claim 5 wherein each of the one or more driver stages comprises a first pull-down driver circuit and a first pull-down driver circuit and adjusting the P/N strength of one or more driver stages of the signal comprises:
adjusting a turn-on delay time of one or more of the first pull-down driver circuits using one or more additional pull-down driver circuits coupled in parallel with one or more of the first pull-down driver circuits; and
adjusting a turn-on delay time of one or more of the first pull-up driver circuits using one or more additional pull-up driver circuits coupled in parallel with one or more of the first pull-up driver circuits.
12. The method of claim 1 wherein determining the signal state duration of the on-chip signal within a range of accuracy using on-chip circuitry comprises:
receiving a data signal using on-chip circuitry at time t 1 , wherein time t 1 is determined by the on-chip signal;
maintaining a state of the data signal for a period T 1 ;
capturing the data signal using the on-chip circuitry at time t 2 , wherein time t 2 is also determined by the on-chip signal; and
comparing a state of the captured data signal with the state of the received data signal to determine a relationship between period T 1 and period T 2 , wherein period T 2 equals t 2 minus t 1 .
13. An integrated circuit comprising circuitry operable to perform the method of claim 1 .
14. An apparatus having one or more on-chip systems to determine and adjust a signal state duration of one or more on-chip signals, the apparatus comprising:
an on-chip signal state duration measuring system having an input to receive an on-chip signal and determine the signal state duration of the on-chip signal within a range of accuracy by comparing the signal state duration of the on-chip signal to a known propagation time of a test data signal; and
an on-chip signal state duration control system coupled to the signal state duration measuring system to receive the determined signal state duration of the on-chip signal and, if the signal state duration of the on-chip signal is not within a predetermined tolerance, to adjust the signal state duration of the on-chip signal to a desired value.
15. The apparatus of claim 14 wherein the signal state duration of the on-chip signal is the pulse-width of the on-chip signal.
16. The apparatus of claim 14 wherein the on-chip signal state duration control system further comprises a comparison circuit to compare the determined signal state duration of the on-chip signal with a desired value.
17. The apparatus of claim 14 further comprising:
a signal state duration adjustment circuit coupled to the on-chip signal state duration control system.
18. The apparatus of claim 17 wherein the signal state duration adjustment circuit comprises:
one or more driver stages to drive and adjust the signal state duration of the on-chip signal in accordance with data received from the on-chip signal state duration control system.
19. The apparatus of claim 18 wherein each of the driver stages comprise:
a first pull-up driver circuit; and
one or more additional pull-up driver circuits coupled in series with the first pull-up driver circuit.
20. The apparatus of claim 18 wherein each of the driver stages comprise:
a first pull-up driver circuit; and
one or more additional pull-up driver circuits coupled in parallel with the first pull-up driver circuit.
21. The apparatus of claim 18 wherein each of the driver stages comprise:
a first pull-down driver circuit; and
one or more additional pull-down driver circuits coupled in parallel with the first pull-down driver circuit.
22. The apparatus of claim 18 wherein each of the driver stages comprise:
a first pull-down driver circuit; and
one or more additional pull-down driver circuits coupled in parallel with the first pull-down driver circuit.
23. The apparatus of claim 18 wherein:
at least one of the driver stages comprises:
a first pull-up driver circuit; and
one or more additional pull-up driver circuits coupled in parallel with the first pull-up driver circuit; and
at least one of the driver stages comprises:
a first pull-down driver circuit; and
one or more additional pull-up driver circuits coupled in parallel with the first pull-down driver circuit.
24. The apparatus of claim 18 wherein:
at least one of the driver stages comprises:
a first pull-up driver circuit; and
one or more additional pull-up driver circuits coupled in series with the first pull-up driver circuit; and
at least one of the driver stages comprises:
a first pull-down driver circuit; and
one or more additional pull-down driver circuits coupled in series with the first pull-down driver circuit.
25. The apparatus of claim 14 wherein the on-chip signal state duration measuring system further comprises:
a first on-chip switch having an input node to receive a data signal at time t 1 and a conductivity control node to receive the on-chip signal;
an on-chip delay circuit having an input node coupled to an output node of the first switch and having a selection node coupled to delay control circuitry;
an on-chip second switch having an input node coupled to an output node of the delay circuit and a conductivity control node to receive the on-chip signal;
an on-chip data signal capture circuit coupled to an output node of the second switch to capture the data signal at time t 2 ; and
a comparison circuit coupled to the first switch and coupled to the data signal capture circuit to compare (a) the data signal received by the first on-chip switch when the on-chip signal at time t 3 causes the first switch to conduct the data signal to (b) the data signal captured by the data signal capture circuit when the on-chip signal subsequently at time t 4 causes the second switch to become nonconductive.
26. An integrated circuit having a system to adjust a signal state duration of an on-chip signal using one or more on-chip systems, the integrated circuit comprising:
on-chip means to determine the signal state duration of the on-chip signal within a range of accuracy;
means, coupled to the means to determine, to compare the signal state duration of the on-chip signal to a known propagation time of a test data signal using a first on-chip system; and
means to adjust the signal state duration towards the desired value using a second on-chip system if the determined signal state duration of the on-chip signal does not have a desired value.
27. The method of claim 26 wherein the signal state duration of the on-chip signal is the pulse-width of the on-chip signal.