IP Library Granted Patent US 7,057,249
Granted Patent B2
US 7,057,249 · App. 10/612,676 · Granted Jun 6, 2006

Magnetic memory device

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Quick Facts
Patent No.
US 7,057,249
App. No.
10/612,676
Granted
Jun 6, 2006
Kind
B2
Abstract

A memory device includes a first surface having memory chips disposed thereon, the memory chips defining an exterior face of the memory device, and a second surface opposite the exterior face. A magnetically permeable shield layer extends over at least one of the exterior face and the second surface of the memory device.

Claims (22)

1. A memory wafer comprising:

a first surface having memory chips disposed thereon, a surface of the memory chips defining an exterior face of the memory wafer;

a second surface opposite the exterior face; and

a magnetically permeable shield layer depositing directly on the entirely of the exterior face of the memory wafer.

2. The memory wafer of claim 1 , wherein the memory chips are separable from the memory wafer.

3. The memory wafer of claim 1 , wherein the memory chips are magnetic random access memory chips.

4. The memory wafer of claim 1 , wherein the memory chips include multiple memory arrays having multiple memory cells.

5. The memory wafer of claim 4 , wherein the memory cells are magnetic random access memory cells.

6. The memory wafer of claim 1 , further comprising bond pads disposed on the memory chips.

7. The memory wafer of claim 6 , wherein the bond pads are electrically accessible via the exterior face of the memory wafer.

8. The memory wafer of claim 1 , wherein the magnetically permeable shield layer comprises a soft magnetic material.

9. The memory wafer of claim 8 , wherein the soft magnetic material is selected from the group consisting of iron, nickel, cobalt, alloys of iron, alloys of nickel, and alloys of cobalt.

10. The memory wafer of claim 1 , wherein the magnetically permeable shield layer has a permeability of greater than 100.

11. The memory wafer of claim 1 , wherein the magnetically permeable shield layer has a coercivity of less than 10 Oersteds.

12. The memory wafer of claim 1 , wherein the magnetically permeable shield layer is isotropic.

13. A memory wafer comprising:

a first surface having memory chips disposed thereon, a surface of the memory chips defining an exterior face of the memory wafer;

a second surface opposite the exterior face; and

means for protecting the memory chips from stray magnetic fields depositing directly on the entirely of the exterior face of the memory wafer.

14. The memory wafer of claim 13 , wherein the means for protecting the memory chips from stray magnetic fields is a magnetically permeable shield layer comprising a soft magnetic material.

15. The memory wafer of claim 14 , wherein the magnetically permeable shield layer has a permeability of greater than 100.

16. The memory wafer of claim 14 , wherein the magnetically permeable shield layer has a coercivity of less than 10 Oersteds.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 22, 2007
From: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 019733/0063 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 31, 2003
From: ANTHONY, THOMAS C.; STOBBS, COLIN A.; BHATTACHARYYA, MANOJ K.; HOLDEN, ANTHONY PETER; BLOOMQUIST, DARREL R.
To: HEWLETT-PACKARD DEVELOPMENT COMPANY, LP
Reel/Frame 013842/0900 →