Multiport memory, data processor and data processing system
View Patent ↗A multiport memory has a plurality of RAMs and a port expansion unit electrically connected to access ports of the RAMs. The port expansion unit includes an input circuit which allows access control information for activating the RAMs in parallel every memory cycles to be collectively inputted thereto by a plurality of memory cycles, a timing generator which generates internal clock signals capable of serially prescribing each memory cycle plural times during one cycle of a clock signal (ck), and a logic circuit capable of sequentially supplying the access control information inputted to the input circuit to the plurality of RAMs in parallel in parts every serial memory cycles synchronized with the internal clock signals. The port expansion unit allows access to the access ports with the plurality of RAMs as a single multiport memory apparently.
1. A semiconductor integrated circuit comprising:
a multiport memory which has a plurality of static RAMs;
a first circuit which receives first address signals and second address signals in parallel in synchronism with a first clock signal; and
a second circuit which supplies said first address signals and said second address signals to each of said static RAMs in serial in synchronism with a second clock signal higher than said first clock signal in frequency,
wherein said plurality of static RAMs are activated in parallel in synchronism with said second clock signal.
2. A semiconductor integrated circuit according to claim 1 ,
wherein two or more cycles of said second clock signal are included in one cycle of said first clock signal,
wherein a read operation from said plurality of static RAMs is performed in a first cycle of said second clock signal, and
wherein a write operation to said plurality of static RAMs is performed in a second cycle subsequent to said first cycle.
3. A semiconductor integrated circuit according to claim 1 ,
wherein two or more cycles of said second clock signal are included in one cycle of said first clock signal,
wherein a first write operation to said plurality of static RAMs is performed in a first cycle of said second clock signal, and
wherein a second write operation to said plurality of static RAMs is performed in a second cycle subsequent to said first cycle.