Method of forming copper wiring in a semiconductor device
View Patent ↗Disclosed is a method of forming a copper wiring in a semiconductor device. A copper barrier metal layer and a copper seed layer are sequentially formed along the surface of an interlayer insulating film including damascene patterns. In a state that a wafer is then loaded onto an electrical plating apparatus in which a copper plating solution is filled and a negative (−) power supply is also applied to the wafer, copper is plated so that the damascene patterns are sufficiently filled, thereby forming a copper layer. Next, the copper layer is polished in the plating solution by means of the electro-polishing process by changing the negative (−) power supply to the positive (+) power supply. Due to this, the surface of the copper layer is flat over the entire wafer. Thereafter, a chemical mechanical polishing process is performed until the surface of the interlayer insulating film is exposed, thereby forming copper wirings within the damascene patterns. As such, an uneven surface of the copper layer plated by the electroplating method is etched in the plating solution, thus making flat the surface of the copper layer and thin the thickness of the copper layer. It is thus possible to prevent a dishing phenomenon or an erosion phenomenon in a subsequent chemical mechanical polishing process. Therefore, the process margin of the chemical mechanical polishing process could be increased and process characteristics could be improved.
1. A method of forming a copper wiring in a semiconductor devices, the method comprising:
forming damascene patterns in an interlayer insulating film which is formed on a substrate;
sequentially forming a copper barrier metal layer and a copper seed layer on the surface of the interlayer insulating film including the damascene patterns;
performing a copper electroplating process in an electroplating apparatus to fill the damascene patterns with a copper layer by applying a negative (−) power supply to the substrate;
performing a copper electro-polishing process to remove the copper layer and the copper seed layer on the interlayer insulating film in the same electroplating apparatus that the copper electroplating process is performed by applying a positive (+) power supply to the copper layer and the copper barrier layer on the interlayer insulating film without the use of a pad so that the copper electro-polishing process is automatically stopped and the copper layer and the copper seed layer is remained in the damascene patterns when the copper barrier metal layer is exposed; and
polishing the copper barrier metal layer on the interlayer insulating film by means of a chemical mechanical polishing process until the surface of the interlayer insulating film is exposed.
2. The method as claimed in claim 1 , wherein the copper barrier metal layer is formed using one of ionized PVD TiN, CVD TiN, MOCVD TiN, ionized PVD Ta, ionized PVD TaN, CVD Ta, CVD TaN and CVD WN.
3. The method as claimed in claim 1 , wherein the copper seed layer is formed using an ionized PVD method.
4. The method as claimed in claim 1 , wherein the copper electroplating process comprises:
loading the substrate on which the copper seed layer is formed onto the electroplating apparatus in which a copper plating solution including an organic accelerator and an organic suppressor are added;
setting a plating target range so that the damascene patterns could be sufficiently filled; and
applying the negative (−) power supply having current in the range of 1˜5 A to the substrate.
5. The method as claimed in claim 1 , wherein the copper electroplating process comprises:
loading the substrate on which the copper seed layer is formed onto the electroplating apparatus in which a copper plating solution including an organic accelerator, an organic suppressor and an organic leveler are added;
setting a plating target range so that the damascene patterns could be sufficiently filled; and
applying the negative (−) power supply having current in a range of 1˜5 A to the substrate.
6. The method as claimed in claim 1 , wherein the copper electro-polishing process is performed by applying the positive (+) power supply having current in a range of 1˜30 A to the copper layer and the copper barrier metal layer.
7. The method as claimed in claim 1 , further comprising detecting that the copper barrier metal layer has been exposed by the electro-polishing process based on detecting an electrical resistance of the copper barrier metal layer.