Failure analysis system and failure analysis method of logic LSI

1. A failure analysis system having software incorporated therein, comprising:

a function to record a test terminal signal information of a testing logic LSI as a target of analysis in synchronization with a clock signal;

a function to reproduce said test recorded terminal signal information in synchronization with the clock signal; and a function to compare said reproduced terminal signal information with a reference terminal signal information of a normal logic LSI,

wherein the test terminal signal information includes a trace data map of a condition change in a register data and a RAM data for a specific period of time.

2. A failure analysis system according to claim 1 , wherein said failure analysis system further has a function to generate a plurality of trace difference maps by generating a plurality of defects and to obtain an average and a data spread of a difference by a statistical work.

3. A failure analysis system according to claim 1 , wherein said failure analysis system further has a function to record a command trace data of a CPU in synchronization with said reference terminal signal information.

4. A failure analysis system according to claim 1 , wherein said failure analysis system further has a function to connect comparative signals of a plurality of logic LSIs to multiinput OR terminals and to analyze a plurality of logic LSIs at the same time.

5. A failure analysis system according to claim 1 , wherein said test terminal signal information also includes an analog signal information.

6. A failure analysis system according to claim 5 , wherein said failure analysis system further has a function to obtain in advance analog/digital difference properties of the testing logic LSI and the normal logic LSI, or digital/analog difference properties thereof and to correct an analog conversion property.

7. A failure analysis system according to claim 5 , wherein said testing logic LSI has an on-chip debugger mounted thereon.

8. A failure analysis system according to claim 1 , wherein said failure analysis system further has layered software.

9. A failure analysis system according to claim 1 , wherein the target of analysis is a system having a logic LSI mounted thereon.

10. A failure analysis method comprising:

recording a test terminal signal information of a testing logic LSI as a target of analysis in synchronization with a clock signal;

reproducing the recorded test terminal signal information in synchronization with the clock signal; and

comparing the reproduced test terminal signal information with a reference terminal signal information of a normal logic LSI,

wherein the test terminal signal information includes a trace data map of a condition change in a register data and a RAM data for a specific period of time.

11. A failure analysis method according to claim 10 , further comprising:

generating a plurality of trace difference maps by generating a plurality of defects; and

obtaining an average and a data spread of a difference by a statistical work.

12. A failure analysis method according to claim 10 , further comprising recording a command trace data of a CPU in synchronization with the reference terminal signal information.

13. A failure analysis method according to claim 10 , further comprising:

connecting a plurality of comparative signals of a plurality of logic LSIs to a plurality of multiinput OR terminals; and

analyzing the plurality of logic LSIs at the same time.

14. A failure analysis method according to claim 10 , wherein the test terminal signal information also includes an analog signal information.

15. A failure analysis method according to claim 14 , further comprising:

obtaining in advance analog/digital difference properties of the testing logic LSI and the normal logic LSI, or digital/analog difference properties thereof; and

correcting an analog conversion property.

16. A failure analysis method according to claim 14 , wherein the testing logic LSI has an on-chip debugger mounted thereon.

17. A failure analysis method according to claim 10 , wherein the target of analysis is a system having a logic LSI mounted thereon.