Semiconductor apparatus
View Patent ↗A semiconductor apparatus is provided in which input/output of an electric signal having a particularly high frequency is less disturbed by parasitic capacitance generated in a wiring in the semiconductor apparatus. A first through-hole wiring penetrating a first dielectric board, a second through-hole wiring penetrating a second dielectric board, and an internal wiring inserted between the first dielectric board and the second dielectric board are provided. The first through-hole wiring and the second through-hole wiring are arranged on the internal wiring while being away from each other.
1. A semiconductor apparatus comprising:
a semiconductor device;
a first dielectric board surrounding said semiconductor device;
a second dielectric board surrounding said semiconductor device and on said first dielectric board;
a metal cover on said second dielectric board and above said semiconductor device;
external electrodes;
upper wiring on said second dielectric board;
first through-hole wiring penetrating said first dielectric board and electrically connected with said external electrodes;
second through-hole wiring penetrating said second dielectric board and electrically connected with said upper wiring; and
internal wiring between said first dielectric board and said second dielectric board,
wherein said semiconductor device is connected with said external electrodes via said first through-hole wiring and said internal wiring, and,
wherein said first through-hole wiring and said second through-hole wiring are electrically connected with said internal wiring while being away from each other.
2. The semiconductor apparatus according to claim 1 , wherein said second through-hole wiring is closer to said semiconductor device than is said first through-hole wiring.
3. The semiconductor apparatus according to claim 2 , wherein
said semiconductor device is connected to said upper wiring via a thin metal wire.
4. The semiconductor apparatus according to claim 3 , further comprising:
a metal plate having said semiconductor device mounted thereon,
wherein said external electrodes and said metal plate are co-planar.
5. The semiconductor apparatus according to claim 3 , wherein said external electrodes are completely arranged within an outer edge of said first dielectric board or said second dielectric board.
6. The semiconductor apparatus according to claim 3 , wherein said external electrodes include an external electrode for grounding, and an upper metal layer supplied with ground potential via said external electrode for grounding is on an upper surface of said second dielectric board.
7. The semiconductor apparatus according to claim 3 , wherein said external electrodes include an external electrode for grounding, and a lower metal layer supplied with ground potential via said external electrode for grounding is on a lower surface of said first dielectric board.
8. The semiconductor apparatus according to claim 4 , wherein said external electrodes are completely arranged within an outer edge of said first dielectric board or said second dielectric board.
9. The semiconductor apparatus according to claim 4 , wherein said external electrodes include an external electrode for grounding, and an upper metal layer supplied with ground potential via said external electrode for grounding is on an upper surface of said second dielectric board.
10. The semiconductor apparatus according to claim 4 , wherein said external electrodes include an external electrode for grounding, and a lower metal layer supplied with a ground potential via said external electrode for grounding is on a lower surface of said first dielectric board.
11. The semiconductor apparatus according to claim 1 , wherein said semiconductor device is connected to said upper wiring via a thin metal wire.
12. The semiconductor apparatus according to claim 11 , further comprising:
a metal plate having said semiconductor device mounted thereon,
wherein said external electrodes and said metal plate are co-planar.
13. The semiconductor apparatus according to claim 11 , wherein said external electrodes are completely arranged within an outer edge of said first dielectric board or said second dielectric board.
14. The semiconductor apparatus according to claim 11 , wherein said external electrodes include an external electrode for grounding, and an upper metal layer supplied with ground potential via said external electrode for grounding is on an upper surface of said second dielectric board.
15. The semiconductor apparatus according to claim 11 , wherein said external electrodes include an external electrode for grounding, and a lower metal layer supplied with a ground potential via said external electrode for grounding is on a lower surface of said first dielectric board.
16. The semiconductor apparatus according to claim 1 , further comprising:
a metal plate having said semiconductor device mounted thereon,
wherein said external electrodes and said metal plate are co-planar.
17. The semiconductor apparatus according to claim 1 , wherein said external electrodes are completely arranged within an outer edge of said first dielectric board or said second dielectric board.
18. The semiconductor apparatus according to claim 1 , wherein said external electrodes include an external electrode for grounding, and an upper metal layer supplied with ground potential via said external electrode for grounding is on an upper surface of said second dielectric board.
19. The semiconductor apparatus according to claim 1 , wherein said external electrodes include an external electrode for grounding, and a lower metal layer supplied with a ground potential via said external electrode for grounding is on a lower surface of said first dielectric board.