Method of manufacturing semiconductor device having thin film SOI structure
View Patent ↗A method of manufacturing a semiconductor device includes the steps of, (1) preparing an SOI substrate, (2) forming a metal layer on the SOI substrate, (3) performing a first anneal treatment to the metal layer at a relatively low temperature in order to transform the metal layer to a first silicide layer, (4) forming an insulating layer on the first silicide layer, and (5) forming a contact hole, which reaches the first silicide layer, in the insulating layer; and (6) performing a second anneal treatment to the silicide layer at a relatively high temperature in order to transform the first silicide layer to a second silicide layer.
1. A method of manufacturing a semiconductor device, comprising:
preparing an SOI substrate;
forming a metal layer on the SOI substrate;
annealing the metal layer at a first temperature, which is effective in converting the metal layer into a first silicide layer;
forming an insulating layer on the first silicide layer; and
forming a hole from a surface of the insulating layer until a part of the first silicide layer is exposed; and
annealing the first silicide layer at a second temperature, which is effective in converting the first silicide layer into a second silicide layer by a rapid thermal annealing process wherein the second temperature is higher than the first temperature.
2. A method as claimed in claim 1 wherein the metal layer includes cobalt.
3. A method as claimed in claim 2 wherein the first silicide layer includes CoSi.
4. A method as claimed in claim 3 wherein the second silicide layer includes CoSi 2 .
5. A method as claimed in claim 1 wherein annealing the metal layer is carried out at a temperature in a range between about 450° C. and about 550° C.
6. A method as claimed in claim 1 wherein annealing the metal layer is carried out at a temperature of about 550° C. for about 30 seconds.
7. A method as claimed in claim 1 wherein the rapid thermal annealing is carried out at a temperature of about 800° C.
8. A method as claimed in claim 1 wherein the SOI substrate has a thickness of 50 nm or less.
9. A method as claimed in claim 1 wherein the hole has a diameter of 0.1 □m or less.
10. A method as claimed in claim 1 wherein a time period of annealing the metal layer is shorter than that of annealing the first silicide layer.
11. A method as claimed in claim 1 wherein a difference between the first temperature and the second temperature is 350° C. or less.
12. A method as claimed in claim 1 wherein a resistance value of the first silicide layer is higher than that of the second suicide layer.