Subranging analog to digital converter with multi-phase clock timing
View Patent ↗An N-bit analog to digital converter includes a reference ladder, a track-and-hold amplifier connected to an input voltage, a coarse ADC amplifier connected to a coarse capacitor at its input and having a coarse ADC reset switch controlled by a first clock phase of a two-phase clock, a fine ADC amplifier connected to a fine capacitor at its input and having a fine ADC reset switch controlled by a second clock phase of the two-phase clock, a switch matrix that selects a voltage subrange from the reference ladder for use by the fine ADC amplifier based on an output of the coarse ADC amplifier, and wherein the coarse capacitor is charged to a coarse reference ladder voltage during the first clock phase and connected to the T/H output during the second clock phase, wherein the fine capacitor is connected to a voltage subrange during the first clock phase and to the T/H output during the second clock phase, and an encoder that converts outputs of the coarse and fine ADC amplifiers to an N-bit output.
1. An analog to digital converter (ADC) comprising:
a first amplifier tracking an input voltage with its output;
a coarse ADC amplifier connected to a coarse capacitor at its input and having a coarse ADC reset switch controlled by a first clock phase;
a fine ADC amplifier connected to a fine capacitor at its input and having a fine ADC reset switch controlled by a second clock phase, wherein a set of reference voltages is selected for use by the fine ADC amplifier based on an output of the coarse ADC amplifier,
wherein the coarse capacitor is charged to a coarse reference voltage during the first clock phase and connected to the first amplifier's output voltage during the second clock phase, and
wherein the fine capacitor is connected to a fine reference voltage during the first clock phase and charged to the first amplifier's output voltage during the second clock phase; and
an encoder that converts outputs of the coarse and fine ADC amplifiers to a digital output.
2. The analog to digital converter of claim 1 , wherein the coarse ADC reset switch is a field effect transistor (FET).
3. The analog to digital converter of claim 1 , wherein the first and second clock phases are non-overlapping.
4. The analog to digital converter of claim 1 , wherein the fine ADC amplifier includes a plurality of cascaded amplifier stages.
5. The analog to digital converter of claim 1 , wherein the coarse ADC amplifier includes a plurality of cascaded amplifier stages.
6. The analog to digital converter of claim 1 , wherein the coarse capacitor is connected to the first amplifier's output on a delayed second phase.
7. The analog to digital converter of claim 1 , wherein the fine ADC capacitor is connected to the first amplifier's output on a delayed second clock phase and to the fine reference voltage during a delayed first clock phase.
8. The analog to digital converter of claim 1 , further including a switch that connects an output of the first amplifier to the coarse capacitor on the second clock phase.
9. The analog to digital converter of claim 1 , further including a coarse comparator that latches the output of the coarse ADC amplifier and outputs it to the encoder.
10. The analog to digital converter of claim 1 , further including a fine comparator that latches the output of the fine ADC amplifier and outputs it to the encoder.
11. The analog to digital converter of claim 1 , wherein the first amplifier is in a hold-mode during the second clock phase.
12. The analog to digital converter of claim 1 , further including a switch matrix to select the set of reference voltages for use by the fine ADC amplifier.
13. An analog to digital converter comprising:
a track-and-hold amplifier tracking an input voltage;
a first plurality of amplifiers each connected to a corresponding capacitor at its input, wherein the amplifiers of the first plurality are reset on a clock phase N 1 and their corresponding capacitors are connected to an output of the track-and-hold on a clock phase N 2 ;
a second plurality of amplifiers each connected to a corresponding capacitor at its input, wherein the amplifiers of the second plurality are reset on the clock phase N 2 and their corresponding capacitors are charged to the track-and-hold amplifier output voltage on the clock phase N 2 and wherein a set of reference voltages is selected based on outputs of the first plurality of amplifiers, for input to the second plurality of amplifiers on the clock phase N 1 ; and
an encoder that converts outputs of the first and second pluralities of amplifiers to a digital output.
14. The analog to digital converter of claim 13 , further including FET switches that reset the first plurality of amplifiers on the clock phase N 1 .
15. The analog to digital converter of claim 13 , wherein the clock phases N 1 and N 2 are non-overlapping.
16. The analog to digital converter of claim 13 , wherein each of the second plurality of amplifiers includes a plurality of cascaded amplifier stages.
17. The analog to digital converter of claim 13 , wherein each of the first plurality of amplifiers includes a plurality of cascaded amplifier stages.
18. The analog to digital converter of claim 13 , wherein the capacitors of the first plurality of amplifiers are connected to the track-and-hold amplifier output on a delayed clock phase N 2 .
19. The analog to digital converter of claim 13 , wherein the capacitors of the second plurality of amplifiers are connected to the track-and-hold amplifier output on a delayed clock phase N 2 , and to the set of reference voltages on a delayed clock phase N 1 .
20. The analog to digital converter of claim 13 , further including switches that connect an output of the track-and-hold to the capacitors of the first plurality of amplifiers on the clock phase N 2 .
21. The analog to digital converter of claim 13 , further including a first plurality of comparators that latch the outputs of the first plurality of amplifiers and output them to the encoder.
22. The analog to digital converter of claim 21 , further including a second plurality of comparators that latch the outputs of the second plurality of amplifiers and output them to the encoder.
23. The analog to digital converter of claim 13 , wherein the track-and-hold amplifier is in a hold-mode on the clock phase N 2 .
24. The analog to digital converter of claim 13 , further including a switch matrix to select the set of reference voltages based on the outputs of the first plurality of amplifiers.
25. An analog to digital converter comprising:
a track-and-hold amplifier tracking an input voltage;
a first amplifier that resets on a clock phase N 1 and amplifies a difference of an output of the track-and-hold amplifier and a first voltage reference on a clock phase N 2 , wherein the track-and-hold amplifier is in a hold-mode on the clock phase N 2 ;
a second amplifier that resets on the clock phase N 2 and amplifies a difference of the output of the track-and-hold amplifier and a second reference voltage on the clock phase N 1 , wherein a first set of reference voltages is selected for use by the second amplifier based on an output of the first amplifier; and
an encoder that converts outputs of the first and second amplifiers to a digital output.
26. The analog to digital converter of claim 25 , wherein the track-and-hold amplifier is in a hold-mode during the clock phase N 2 .
27. The analog to digital converter of claim 25 , further including a switch matrix to select the set of reference voltages for use by the second amplifier.