IP Library Granted Patent US 7,397,503
Granted Patent B2
US 7,397,503 · App. 10/629,083 · Granted Jul 8, 2008

Systems and methods for reducing artifacts caused by illuminant flicker

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Quick Facts
Patent No.
US 7,397,503
App. No.
10/629,083
Granted
Jul 8, 2008
Kind
B2
Abstract

Methods for reducing artifacts caused by illuminant flicker are provided. One such method comprises: providing pixel circuits; and operating the pixel circuits in a bi-directional mode during which first information corresponding to a scene is acquired in forward row-sequential order of the pixel circuits and then second information corresponding to the scene is acquired in a reverse row-sequential order of the pixel circuits. Systems also are provided.

Claims (40)

1. A system for reducing artifacts caused by illuminant flicker, said system comprising:

an image sensor comprising an array of pixel circuits arranged in rows, a first of the pixel circuits being located in a first of the rows, a second of the pixel circuits being located in a second of the rows, the first of the pixel circuits being operable to acquire first information corresponding to the scene at a first time, the second of the pixel circuits being operable to acquire second information corresponding to the scene at a second time subsequent to the first time and to acquire third information corresponding to the scene at a third time subsequent to the second time, the first of the pixel circuits being further operable to acquire fourth information corresponding to the scene at a fourth time subsequent to the third time;

the image sensor being operable to combine the first information and the fourth information to provide a first output signal corresponding to the first of the pixel circuits, and to combine the second information and the third information to provide a second output signal corresponding to the second of the pixel circuits.

2. The system of claim 1 , wherein the first of the rows of pixel circuits is located adjacent to the second of the rows of pixel circuits.

3. The system of claim 1 further comprising:

a controller operable to provide an input signal to the image sensor to set timing of a reset and read operations of the rows of pixel circuits; and

flicker detector operable to provide the controller with a signal corresponding to detected amount of flicker artifact acquired by the array.

4. A system for reducing artifacts caused by illuminant flicker, said system comprising:

an array of pixel circuits operable in a bi-directional mode during which the array acquires first information corresponding to a scene in forward row-sequential order of the pixel circuits and then acquires second information corresponding to the scene in reverse row-sequential order of the pixel circuits; and

an image processor operable to receive the first information and the second information and to combine the first information and the second information to provide an output signal corresponding to the scene.

5. The system of claim 4 , wherein at least one of the pixel circuits comprises a complimentary metal oxide semiconductor (CMOS) pixel circuit.

6. The system of claim 5 , wherein the at least one of the pixel circuits comprises a 3 T pixel circuit.

7. The system of claim 4 , wherein the array of pixel circuits has a detection cycle having a duration corresponding to a duration of the flicker cycle of the illuminant.

8. The system of claim 7 , wherein the detection cycle is temporally aligned with the flicker cycle of the illuminant.

9. The system of claim 4 , wherein the array of pixel circuits is further operable in a uni-directional mode during which the array acquires information corresponding to the scene only in the forward row-sequential order of the pixel circuits.

10. The system of claim 9 , further comprising:

a controller operable to provide an input signal to the array of pixel circuits, the input signal selectively causing the array to operate in either the bi-directional mode or the unidirectional mode.

11. The system of claim 9 , further comprising:

means for selectively causing the array to operate in either the bi-directional mode or the uni-directional mode.

12. The system of claim 10 , further comprising:

a flicker detector communicating with the controller and operable to provide the controller with a signal corresponding to a detected amount of flicker artifact acquired by the array.

13. A method for reducing artifacts caused by illuminant flicker captured by an image reception device having pixel circuits, said method comprising:

capturing a plurality of images by operating the pixel circuits in the image reception device in a bi-directional mode during which first information corresponding to a scene is acquired in forward row-sequential order of the pixel circuits and then second information corresponding to the scene is acquired in reverse row-sequential order of the pixel circuits; and

detecting, by a flicker detector, flicker artifacts in the plurality of captured images;

outputting, by the flicker detector, a flicker signal indicative of an increase or a decrease of the illuminant flicker in each subsequently captured image; and

controlling a timing of a detection cycle of the pixel circuits to decrease flicker in each subsequently captured image.

14. The method of claim 13 , further comprising:

combining the first information and the second information to form frames of image information corresponding to the pixel circuits.

15. The method of claim 13 , wherein a duration of a detection cycle of the pixel circuits corresponds to acquisition of the first information and acquisition of the second information; and further comprising:

aligning the detection cycle with a flicker cycle of the illuminant.

16. A method for reducing, in pixel circuits, artifacts caused by illuminant flicker by an illuminant exhibiting an illuminant waveform defining a flicker cycle, said method comprising:

operating the pixel circuits in a bi-directional mode during which first information corresponding to a scene is acquired in forward row-sequential order of the pixel circuits and then second information corresponding to the scene is acquired in reverse row-sequential order of the pixel circuit such that a duration of a detection cycle of the pixel circuits corresponds to acquisition of the first information and acquisition of the second information;

aligning the detection cycle with the flicker cycle of the illuminant;

and

wherein, in aligning the detection cycle, a first time period during which the first information is acquired corresponds to a first portion of the illuminant waveform, and a second time period during which the second information is acquired corresponds to a second portion of the illuminant waveform, demarcation of the first portion and the second portion of the illuminant waveform occurring at a location of symmetry of the illuminant waveform about an arbitrary illumination level.

17. The method of claim 16 , further comprising:

detecting flicker artifact in the information acquired; and

adjusting the duration of the detection cycle of the pixel circuits to reduce the flicker artifact in subsequently acquired information.

18. The method of claim 16 , further comprising:

selectively operating the pixel in either the bi-directional mode or a uni-directional mode, during which information corresponding to the scene is only acquired in the forward row-sequential order of the pixel circuits.

Assignments (8)
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE NAME PREVIOUSLY RECORDED AT REEL: 017206 FRAME: 0666. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded May 6, 2016
From: AGILENT TECHNOLOGIES, INC.
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 038632/0662 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 30, 2010
From: MICRON TECHNOLOGY, INC.
To: APTINA IMAGING CORPORATION
Reel/Frame 024160/0051 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 1, 2008
From: AVAGO TECHNOLOGIES SENSOR IP PTE. LTD.
To: AVAGO TECHNOLOGIES IMAGING HOLDING CORPORATION
Reel/Frame 021603/0690 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 7, 2007
From: AVAGO TECHNOLOGIES IMAGING HOLDING CORPORATION
To: MICRON TECHNOLOGY, INC.
Reel/Frame 019407/0441 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 3, 2007
From: AVAGO TECHNOLOGIES IMAGING HOLDING CORPORATION
To: MICRON TECHNOLOGY, INC.
Reel/Frame 018757/0159 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 22, 2006
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES SENSOR IP PTE. LTD.
Reel/Frame 018545/0426 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 22, 2006
From: AGILENT TECHNOLOGIES, INC.
To: AVAGO TECHNOLOGIES GENERAL IP PTE. LTD.
Reel/Frame 017206/0666 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 6, 2003
From: BAER, RICHARD L.; KAKARALA, RAMAKRISHNA
To: AGILENT TECHNOLOGIES, INC.
Reel/Frame 014110/0953 →