Porous polyurethane polishing pads
View Patent ↗A porous polishing pad is useful for polishing semiconductor substrates. The porous polishing pad has a porous matrix formed from a coagulated polyurethane and a non-fibrous polishing layer. The non-fibrous polishing layer has a polishing surface with a pore count of at least 500 pores per mm 2 that decreases with removal of the polishing layer; and the polishing surface has a surface roughness Ra between 0.01 and 3 μm.
1. A method of polishing a patterned semiconductor substrate including the step of polishing the semiconductor substrate with a porous polishing pad, the porous polishing pad having a porous matrix formed from a coagulated polyurethane and a non-fibrous polishing layer, the non-fibrous polishing layer having a polishing surface with a pore count of at least 500 pores per mm 2 and the pore count (per mm 2 ) decreases below the polishing layer and a surface roughness Ra between 0.01 and 3 μm and maintaining the polishing surface with the pore count of at least 500 pores per mm 2 for at least 50 patterned wafers.
2. The method of claim 1 including the additional step of conditioning the porous polishing pad with a polymeric brush or polymeric pad.
3. The method of claim 1 wherein the polishing occurs with a surface, roughness Ra between 0.1 and 2 μm.
4. The method of claim 1 including the additional step of applying a cutting tool to the upper surface.
5. The method of claim 4 wherein the applying a cutting tool includes pressing a diamond conditioning head against the upper surface.
6. A method of polishing a patterned semiconductor substrate including the step of polishing the semiconductor substrate with a porous polishing pad, the porous polishing pad having a porous matrix formed from a coagulated polyurethane and a non-fibrous polishing layer, the non-fibrous polishing layer having a polishing surface with a pore count of at least 500 pores per mm 2 and the pore count (per mm 2 ) decreases below the polishing layer and a surface roughness Ra between 0.01 and 3 μm and maintaining the polishing surface with the pore count of 500 to 10,000 pores per mm 2 for at least 50 patterned wafers.
7. The method of claim 6 wherein the porous polishing pad maintains a pore count of 500 to 2,500 pores per mm 2 for at least 50 patterned wafers.
8. The method or claim 6 including the additional stop of conditioning the porous polishing pad with a polymeric brush or polymeric pad.
9. The method of claim 6 wherein the polishing occurs with a surface roughness Ra between 0.1 and 2 μm.
10. The method of claim 6 including the additional step of applying a cutting tool to the upper surface.
11. The method of claim 10 wherein the applying a cutting tool includes pressing a diamond conditioning head against the upper surface.