Superconducting integrated circuit and method for fabrication thereof
View Patent ↗A superconducting integrated circuit includes a substrate, a multilayer structure formed on the substrate and composed of a lower superconducting electrode, a tunnel barrier and an upper superconducting electrode sequentially joined together upward in the order mentioned, and an insulating layer perforated to form via holes to get electrical contacts with the lower and upper electrodes. The insulating layer is formed of a high-resolution, photosensitive, solvent-soluble, organic insulating material. The superconducting integrated circuit is produced by a method that includes the steps of depositing the multiplayer on the substrate, applying the insulating material to the front surface of the substrate inclusive of the multiplayer, forming the via holes in the insulating material by the lithographic technique at the prospective positions to get electrical contacts with the upper and lower electrodes, and laying wirings for connecting the upper and lower electrodes through the via holes.
1. A superconducting integrated circuit comprising:
a substrate;
a multilayer structure formed on said substrate and composed of a lower Nb superconducting electrode, a tunnel barrier and an upper Nb superconducting electrode sequentially joined together upward in the order mentioned; and
an insulating layer perforated to form via holes to get electrical contacts with said lower electrode and said upper electrode, said insulating layer being formed of a high-resolution, photosensitive, solvent-soluble block-copolyimide.
2. The superconducting integrated circuit according to claim 1 , further comprising a resistor additionally disposed on said substrate and a via hole formed in said insulating layer to get electrical contacts with said resistor.
3. The superconducting integrated circuit according to claim 1 , wherein a temperature of a heat treatment for forming said insulating layer is in a range of 120° C. to 150° C.
4. The superconducting integrated circuit according to claim 1 , wherein the insulating layer is between the substrate and the lower Nb superconducting electrode.
5. The superconducting integrated circuit according to claim 4 , wherein the insulating layer is between a superconducting wiring layer and the upper Nb superconducting electrode.