Nonvolatile memory cells with buried channel transistors
View Patent ↗In a nonvolatile memory cell ( 110 ), the select gate transistor is formed as a buried channel transistor to increase the transistor current.
1. A method for manufacturing an integrated circuit comprising a nonvolatile memory cell having source/drain regions of a first conductivity type in a semiconductor substrate and having a channel region in the semiconductor substrate between the source/drain regions, the method comprising:
forming a first conductive gate comprising a semiconductor material of a second conductivity type opposite to the first conductivity type, the first conductive gate overlying a portion of the channel region; and
forming a floating gate overlying a portion of the channel regions;
wherein the channel region comprises a surface region underlying the first conductive gate and having a lower net dopant concentration of the second conductivity type than a region immediately below the surface region.
2. The method of claim 1 wherein the first conductive gate is a gate of a buried channel transistor.
3. The method of claim 1 , wherein the surface region is at most 0.2 μm deep.
4. The method of claim 1 further comprising implanting an impurity of the first conductivity type into surface region.
5. The method of claim 4 wherein the surface region is at most 0.2 μm deep.
6. The method of claim 1 wherein the channel region has the second conductivity type.
7. The method of claim 1 wherein the first conductive gate is to turn on the underlying portion of the channel region to provide access to the nonvolatile memory cell.
8. The method of claim 1 wherein the floating gate is one of two floating gates of the nonvolatile memory cell, each floating gate overlying a portion of the channel region.
9. The method of claim 1 wherein the first conductivity type is type N.
10. The method of claim 1 wherein the first conductivity type is type P.
11. A method for manufacturing an integrated circuit comprising a nonvolatile memory cell having source/drain regions of a first conductivity type in a semiconductor substrate and having a channel region in the substrate between the source/drain regions, the method comprising:
forming a first conductive gate overlying a portion of the channel region; and
forming a floating gate overlying a portion of the channel region;
wherein the first conductive gate is a gate of a buried channel transistor;
wherein the channel region comprises a surface region underlying the first conductive gate and having a lower net dopant concentration of the second conductivity type than a region immediately below the surface region.
12. The method of claim 11 wherein the surface region is at most 0.2 μm deep.
13. The method of claim 11 further comprising implanting an impurity of the first conductivity type into the surface region.
14. The method of claim 13 wherein the surface region is at most 0.2 μm deep.
15. The method of claim 11 wherein the channel region has the second conductivity type.
16. The method of claim 11 wherein the first conductive gate is to turn on the underlying portion of the channel portion to provide access to the memory cell.
17. The method of claim 11 wherein the floating gate is one of two floating gates of the memory cell, each floating gate overlying a portion of the channel region.
18. The method of claim 11 wherein the first conductivity type is type N.
19. The method of claim 11 wherein the first conductivity type is type P.