Patent Assignment
Reel/Frame 015483/0947
Assignment of Assignor's Interest
Recorded: 2004-07-01
Received: 2004-07-06
Pages: 5
Assignor
MOSEL VITELIC, INC.
Executed: 2004-06-22
Assignee
PROMOS TECHNOLOGIES INC.
3F, NO. 19, LI-HSIN ROAD, SCIENCE-BASED INDUSTRIAL PARK, HSIN-CHU CITY, TWX, TAIWAN
Covered Properties
(63)
Fabrication of Gate Dielectric in Nonvolatile Memories Having Select, Floating and Control Gates
Application:
10/803,599 →
Two Stage Etching of Silicon Nitride to Form a Nitride Spacer
Application:
10/800,190 →
Use of Multiple Etching Steps to Reduce Lateral Etch Undercut
Application:
10/772,932 →
Use of Pedestals to Fabricate Contact Openings
Application:
10/772,520 →
Floating Gate Nitridation
Application:
10/769,025 →
Substrate Isolation in Integrated Circuits
Application:
10/732,616 →
Precision Creation of Inter-Gates Insulator
Application:
10/718,008 →
Dynamically Controllable Reduction of Vertical Contact Diameter Through Adjustment of Etch Mask Stack for Dielectric Etch
Application:
10/718,320 →
Formation of a Double Gate Structure
Application:
10/702,711 →
Method for Providing Representative Features for Use in Inspection of Photolithography Mask and for Use in Inspection Photo-Lithographically Developed and/or Patterned Wafer Layers, and Products of Same
Application:
10/702,527 →
Nonvolatile Memory Structures and Fabrication Methods
Application:
10/689,908 →
Nonvolatile Memory Fabrication Methods Comprising Lateral Recessing of Dielectric Sidewalls at Substrate Isolation Regions
Application:
10/678,317 →
Multi-Tool, Multi-Slurry Chemical Mechanical Polishing
Application:
10/677,785 →
Floating gate memory structures and fabrication methods
Application:
10/658,934 →
Control of Air Gap Position in a Dielectric Layer
Application:
10/655,706 →
Corner Protection to Reduce Wrap Around
Application:
10/655,705 →
Methods of reducing or removing micromasking residue prior to metal etch using oxide hardmask
Application:
10/649,099 →
Electronic Memory Having Impedance-Matched Sensing
Application:
10/640,929 →
Electronic Memory Such as Flash Eprom with Bitwise-Adjusted Writing Current or/and Voltage
Application:
10/640,928 →
Nonvolatile Memories and Methods of Fabrication
Application:
10/631,552 →
Fabrication of Gate Dielectric in Nonvolatile Memories in Which a Memory Cell Has Multiple Floating Gates
Application:
10/632,154 →
Fabrication of Dielectric for a Nonvolatile Memory Cell Having Multiple Floating Gates
Application:
10/631,452 →
Nonvolatile Memory Cell with Multiple Floating Gates Formed After the Select Gate and Having Upward Protrusions
Application:
10/632,186 →
Arrays of Nonvolatile Memory Cells Wherein Each Cell Has Two Conductive Floating Gates
Application:
10/632,007 →
Nonvolatile Memory Cells with Buried Channel Transistors
Application:
10/632,155 →
Nonvolatile Memory Cell with Multiple Floating Gates Formed After the Select Gate
Application:
10/631,941 →
Methods for Improving Quality of Semiconductor Oxide Composition Formed from Halogen-Containing Precursor
Application:
10/442,759 →
Fabrication of Dielectric on a Gate Surface to Insulate the Gate from Another Element of an Integrated Circuit
Application:
10/440,005 →
Fabrication of Gate Dielectric in Nonvolatile Memories Having Select, Floating and Control Gates
Application:
10/440,508 →
Fabrication of Conductive Gates for Nonvolatile Memories from Layers with Protruding Portions
Application:
10/440,466 →
Methods of Fabricating Integrated Circuits with Openings That Allow Electrical Contact to Conductive Features Having Self-Aligned Edges
Application:
10/440,500 →
Nonvolatile Memory Structures and Fabrication Methods
Application:
10/434,262 →
Method for Forming a Protective Buffer Layer for High Temperature Oxide Processing
Application:
10/423,162 →
Nonvolatile Memories with a Floating Gate Having an Upward Protrusion
Application:
10/411,813 →
Nonvolatile Memory with Pedestals
Application:
10/402,698 →
Method for etching a titanium-containing layer prior to etching an aluminum layer in a metal stack
Application:
10/402,745 →
Nonvolatile Memories and Methods of Fabrication
Application:
10/393,212 →
Fabrication of Integrated Circuit Elements in Structures with Protruding Features
Application:
10/393,202 →
Method of Making a Silicon Nitride Film That Is Transmissive to Ultraviolet Light
Application:
10/373,917 →
Comparison of Chemical-Mechanical Polishing Processes
Application:
10/309,473 →
Photolithography Method Including a Double Exposure/Double Bake
Application:
10/306,397 →
Trench Isolation Without Grooving
Application:
10/305,464 →
Forming Conductive Layers on Insulators by Physical Vapor Deposition
Application:
10/300,231 →
Floating gate memory structures and fabrication methods
Application:
10/266,378 →
Floating Gate Memory Fabrication Methods Comprising a Field Dielectric Etch with a Horizontal Etch Component
Application:
10/262,785 →
Polishing System Including a Hydrostatic Fluid Bearing Support
Application:
10/253,738 →
Nonvolatile Memory Cell with a Floating Gate at Least Partially Located in a Trench in a Semiconductor Substrate
Application:
10/252,143 →
Method for Forming a Protective Buffer Layer for High Temperature Oxide Processing
Application:
10/243,791 →
Atomic Layer Deposition of Interpoly Oxides in a Non-Volatile Memory Device
Application:
10/243,379 →
Method of Etching a Dielectric Material in the Presence of Polysilicon
Application:
10/202,992 →
Nonvolatile Memory Structures and Fabrication Methods
Application:
10/200,443 →
Two Stage Etching of Silicon Nitride to Form a Nitride Spacer
Application:
10/198,825 →
Floating gate nitridation
Application:
10/184,661 →
Method for Fabricating an Integrated Circuit with a Transistor Electrode
Application:
10/136,498 →
Thin Titanium Nitride Layers Used in Conjunction with Tungsten
Application:
10/109,212 →
HDP CVD process for void-free gap fill of a high aspect ratio trench
Application:
10/080,468 →
Floating gate nitridation
Application:
10/071,689 →
Multiple Photolithographic Exposures with Different Non-Clear Patterns
Application:
10/058,174 →
Cobalt Silicide Fabrication Using Protective Titanium
Application:
10/056,154 →
Multiple Photolithographic Exposures with Different Clear Patterns
Application:
10/020,452 →
Reduced Thickness Variation in a Material Layer Deposited in Norrow and Wide Integrated Circuit Trenches
Application:
10/033,114 →
Determining an Endpoint in a Polishing Process
Application:
09/976,331 →
Nonvolatile Memory Structures and Fabrication Methods
Application:
09/969,841 →