Nonvolatile memories and methods of fabrication
View Patent ↗To fabricate a nonvolatile memory, a select gate ( 140 ) is formed over a semiconductor substrate. A dielectric ( 810, 1010, 1030 ) is formed over the select gate. A floating gate layer ( 160 ), e.g. doped polysilicon, is formed over the select gate. The floating gate layer is removed from over at least a portion of the select gate. A dielectric ( 1510 ), e.g., ONO, is formed over the floating gate layer, and a control gate layer ( 170 ) is formed over this dielectric. The control gate layer has an upward protrusion over the select gate. Then another layer ( 1710 ), e.g. silicon nitride, is formed on the control gate layer, but the protrusions of the control gate layer are exposed. The exposed portion of the control gate layer is etched selectively until the control gate layer is removed from over at least a portion of the select gate. Then another layer ( 1910 ) is formed on the exposed portion of the control gate layer. This is thermally grown silicon dioxide in some embodiments. Then the silicon nitride is removed. The control gate layer, the ONO, and the floating gate layer are etched selectively to the silicon dioxide to define the control and floating gates. Other embodiments are also provided.
1. A method for fabricating an integrated circuit which comprises a nonvolatile memory cell comprising a first conductive gate, a second conductive gate, and a conductive floating gate which are insulated from each other, the method comprising:
(a) forming the first conductive gate over a semiconductor substrate, and forming a dielectric over a sidewall of the first conductive gate to insulate the first conductive gate from the floating gate;
(b) forming an FG layer over the first conductive gate, wherein the floating gate comprises a portion of the FG layer;
(c) removing the FG layer from over at least a portion of the first conductive gate;
(d) forming a second conductive gate layer over the FG layer to provide at least a portion of the second conductive gate, the second conductive gate layer having a portion P 1 protruding above the first conductive gate;
(e) forming a first layer L 1 over the second conductive gate layer such that the protruding portion P 1 is exposed and not completely covered by the first layer L 1 ;
(f) partially removing the second conductive gate layer at the location of the portion P 1 selectively to the first layer L 1 to remove the second conductive gate layer from over at least a portion of the first conductive gate;
(g) forming a second layer L 2 on the second conductive gate layer adjacent to the first conductive gate; and
(h) removing at least parts of the first layer L 1 , the second conductive gate layer and the FG layer selectively to the second layer L 2 .
2. The method of claim 1 wherein the operation (g) comprises reacting the second conductive gate layer with another material to form the second layer L 2 .
3. The method of claim 2 wherein the reacting operation comprises oxidation of the second conductive gate layer.
4. The method of claim 2 wherein the reacting operation comprises a chemical reaction of the second conductive gate layer with a metal, and the chemical reaction is followed by removal of non-reacted metal.
5. The method of claim 1 further comprising removing the first layer L 1 , the second conductive layer and the FG layer on a first side of the first conductive gate but not a second side of the first conductive, gate, the second side being opposite to the first side.
6. The method of claim 5 further comprising forming a first source/drain region for the memory cell in the semiconductor substrate adjacent to the floating gate on the second side of the first conductive gate, and forming a second source/drain region for the memory cell in the semiconductor substrate adjacent to the first conductive gate on the first side of the first conductive gate.
7. The method of claim 1 wherein the memory cell is part of an array of memory cells each of which comprises a first conductive gate, a second conductive gate, and a floating gate that are insulated from each other;
wherein the operation (a) comprises forming one or more first conductive lines each of which provides at least a portion of each of a plurality of the first conductive gates;
wherein each floating gate comprises at least a portion of the FG layer;
wherein the operation (c) removes the FG layer from over at least a portion of each first conductive gate;
wherein the second conductive gate layer provides at least a portion of each second conductive gate;
wherein at a conclusion of the operation (d) the second conductive gate layer comprises a portion protruding above each first conductive gate;
wherein at a conclusion, of the operation (e) the second conductive gate layer is exposed over each first conductive gate;
wherein the operation (f) partially removes the second conductive gate layer from over at least a portion of each first conductive gate;
wherein the operation (g) forms the second layer L 2 on the second conductive gate layer adjacent to each first conductive gate.