Patent Assignment
Reel/Frame 026795/0164
Assignment of Assignor's Interest
Recorded: 2011-08-22
Received: 2011-08-22
Pages: 17
Assignor
PROMOS TECHNOLOGIES INC.
Executed: 2011-08-04
Assignee
CHANG LIAO HOLDINGS, LLC
2711 CENTERVILLE ROAD, SUITE 400, WILMINGTON, DE, 19808, UNITED STATES
Covered Properties
(46)
Manufacturing Method of Dynamic Random Access Memory
Application:
12/111,980 →
Flash memory structure and method for fabricating the same
Application:
12/010,827 →
Non-Volatile Memory
Application:
11/668,477 →
Deep Trench Capacitor
Application:
11/565,633 →
Method for preparing a capacitor structure of a semiconductor memory
Application:
11/438,396 →
Methods for Improving Quality of High Temperature Oxide (Hto) Formed from Halogen-Containing Precursor and Products Thereof and Apparatus Therefor
Application:
11/431,087 →
A Dynamic Random Access Memory Device
Application:
11/307,424 →
Flash Memory Structure and Method for Fabricating the Same
Application:
11/302,122 →
Method for Fabricating Memory Cell
Application:
11/298,836 →
Flash memory structure and method for fabricating the same
Application:
11/288,194 →
Bottle-shaped trench and method of fabricating the same
Application:
11/267,163 →
Method for preparing a deep trench
Application:
11/222,966 →
Fabrication Method of a Non-Volatile Memory
Application:
11/161,724 →
Nonvolatile Memories and Methods of Fabrication
Application:
11/112,702 →
Method for Preparing a Structure with High Aspect Ratio
Application:
11/078,435 →
Method of Fabricating Deep Trench Capacitor"
Application:
10/904,479 →
Stack-Film Trench Capacitor and Method for Manufacturing the Same
Application:
10/965,160 →
Method of Forming Deep Trench Capacitors
Application:
10/962,473 →
Apparatus and process for physical vapor deposition
Application:
10/930,239 →
Control of Air Gap Position in a Dielectric Layer
Application:
10/921,041 →
Formation of Removable Shroud by Anisotropic Plasma Etch
Application:
10/877,591 →
Method for Removal of Hemispherical Grained Silicon in a Deep Trench
Application:
10/758,624 →
[Method of Fabricating Deep Trench Capacitor]
Application:
10/707,357 →
Trench Capacitor and Process for Preventing Parasitic Leakage
Application:
10/681,125 →
Control of Air Gap Position in a Dielectric Layer
Application:
10/655,706 →
Nonvolatile Memories and Methods of Fabrication
Application:
10/631,552 →
Methods for Improving Quality of Semiconductor Oxide Composition Formed from Halogen-Containing Precursor
Application:
10/442,759 →
Trench capacitor process for preventing parasitic leakage
Application:
10/404,430 →
Nonvolatile Memories and Methods of Fabrication
Application:
10/393,212 →
Stack-Film Trench Capacitor and Method for Manufacturing the Same
Application:
10/331,612 →
Trench Capacitor with Expanded Area and Method of Making the Same
Application:
10/317,912 →
Method and Device for Providing Double Cell Density in Sdram and in Ddr Sdram
Application:
10/272,312 →
Method of Forming Contact Hole
Application:
10/262,939 →
Polishing System Including a Hydrostatic Fluid Bearing Support
Application:
10/253,738 →
Fabrication of Dielectric in Trenches Formed in a Semiconductor Substrate for a Nonvolatile Memory
Application:
10/174,442 →
Method for preventing shorts between contact windows and metal lines
Application:
10/097,052 →
Method for Measuring the Depth of Well
Application:
10/074,852 →
Buried Strap Formation Method for Sub-150 Nm Best Dram Devices
Application:
10/020,754 →
Self-Aligned Active Array Along the Length Direction to Form Un-Biased Buried Strap Formation for Sub-150 Nm Best Dram Devices
Application:
10/002,983 →
Memory Cell Having a Deep Trench Capacitor and a Vertical Channel
Application:
09/983,681 →
Method and System for Determining the Best Integral Process Path to Process Semiconductor Products to Improve Yield
Application:
09/900,165 →
Apparatus and Method for Determining Various Processes of Wafer Fabrication in a Semiconductor Device Manufacturing Technology
Application:
09/894,753 →
Mos Transistors Having Dual Gates and Self-Aligned Interconnect Contact Windows
Application:
09/896,205 →
Teaching Tool for a Robot Arm for Wafer Reaction Ovens
Application:
09/863,329 →
New Poly Spacer Split Gate Cell with Extremely Small Cell Size
Application:
09/822,563 →
Addition of Planarizing Dielectric Layer to Reduce a Dishing Phenomena Experienced During a Chemical Mechanical Procedure Used in the Formation of Shallow Trench Isolation Regions
Application:
09/759,905 →