Trench capacitor and process for preventing parasitic leakage
View Patent ↗A trench capacitor process for preventing parasitic leakage. The process is capable of blocking leakage current from a parasitic transistor adjacent to the trench, and includes the steps of forming a doping layer and a cap layer covering portions of the sidewall of the trench and performing an annealing process on the doping layer to form a dopant region in the substrate adjacent to each sidewall of the trench and blocks leakage current from a parasitic transistor adjacent to the trench.
1. A trench capacitor process for preventing parasitic leakage, comprising the steps of:
providing a substrate with a trench formed therein, wherein the trench has a buried plate formed adjacent to the lower portion thereof;
forming a dielectric layer and a first conductive layer in the lower portion of the trench, wherein the buried plate and the first conductive layer are separated by the dielectric layer;
conformably depositing a layer of doping material on the substrate, the sidewalls in the upper portion of the trench and the dielectric layer and the first conductive layer in the lower portion of the trench;
removing the portion of the doping material on the substrate and the dielectric layer and the first conductive layer in the lower portion of the trench to leave a doping layer on sidewalls of the trench;
forming a protective plug in the trench to expose a portion of the doping layer; removing the portion of the doping layer exposed by the protective plug;
removing the protective plug to form a doping layer on portions of each sidewall of the trench above the dielectric layer and the first conductive layer;
forming a cap layer on each exposed sidewall and each doping layer;
performing an annealing process on each doping layer to form a dopant region in the adjacent substrate, wherein each dopant region blocks leakage current resulting from a parasitic transistor adjacent to the trench and has a first distance from the surface of the substrate;
forming a second conductive layer in the trench to expose portions of the cap layers, wherein the second conductive layer contacts the first conductive layer and has substantially the same height with respect to the dopant regions;
removing portions of the cap layers exposed by the second conductive layer to reveal portions of the sidewalls in the upper portion of the trench; and
forming a third conductive layer on the second conductive layer to fill the trench, wherein the third conductive layer directly contacts the exposed sidewalls in the upper portions of the trench.
2. The trench capacitor process as claimed in claim 1 , wherein the substrate is a p-substrate.
3. The trench capacitor process as claimed in claim 1 , wherein the dielectric layer is nitride material.
4. The trench capacitor process as claimed in claim 3 , wherein the nitride material is silicon nitride.
5. The trench capacitor process as claimed in claim 1 , wherein the buried plate is an n-doped region in the substrate adjacent to the lower portion of the trench.
6. The trench capacitor process as claimed in claim 1 , wherein the first conductive layer, the second conductive layer and the third conductive layer are n-doped polysilicon.
7. The trench capacitor process as claimed in claim 6 , wherein the n-doped polysilicon is arsenic-doped polysilicon.
8. The trench capacitor process as claimed in claim 1 , wherein the doping layer is boro-silicate-glass (BSG).
9. The trench capacitor process as claimed in claim 1 , wherein the cap layer is silicon dioxide.
10. The trench capacitor process as claimed in claim 1 , wherein the doping region is vertically distributed in the substrate adjacent to the trench and approximately equidistant from the trench.
11. The trench capacitor process as claimed in claim 1 , wherein the annealing process is furnace annealing or rapid thermal annealing (RTA).
12. The trench capacitor process as claimed in claim 1 , wherein the charging conductivity of the dopants in the doping region is the same as in the substrate.
13. The trench capacitor process as claimed in claim 1 , wherein the concentration of the dopants in the doping region is about double that in the substrate.
14. The trench capacitor process as claimed in claim 1 , wherein the first distance is about 500˜2500 Å.
15. A trench capacitor process for preventing parasitic leakage, capable of blocking leakage current resulting from a parasitic transistor adjacent to the trench, comprising the steps of:
conformably depositing a doping layer over the sidewalls of the trench;
forming a protective plug in the trench to expose a portion of the doping layer;
removing the portion of the doping layer exposed by the protective plug;
removing the protective plug to form a doping layer covering part of the sidewall of the trench;
forming a cap layer on the doping layer; and
performing an annealing process on the doping layer and forming a dopant region in the substrate adjacent to the sidewall of the trench to block leakage current resulting from a parasitic transistor adjacent to the trench.
16. The trench capacitor process as claimed in claim 15 , wherein the doping layer is boro-silicate-glass (BSG).
17. The trench capacitor process as claimed in claim 15 , wherein the cap layer is silicon dioxide.
18. The trench capacitor process for preventing parasitic leakage as claimed in claim 15 , wherein the charging conductivity of the dopants in the doping region is the same as that in the substrate.
19. The trench capacitor process as claimed in claim 15 , wherein the concentration of the dopants in the doping region is about double that in the substrate.
20. The trench capacitor process as claimed in claim 15 , wherein the dopant region does not contact the surface of the substrate and has a first distance therebetween.
21. The trench capacitor process as claimed in claim 20 , wherein the first distance is about 500˜2500 Å.