Flash memory structure and method for fabricating the same
A flash memory structure comprises a silicon substrate having at least one concave structure, two doped regions positioned in the semiconductor substrate and at two sides of the concave structure, at least one carrier trapping region positioned in the concave structure, and a conductive layer positioned above the concave structure. The concave structure comprises two grooves having a U-shaped or V-shaped profile. The grooves have an inclined plane with (111) orientation and a bottom plane with (100) orientation of the silicon substrate. The carrier trapping region comprises a dielectric stack positioned in the concave structure, wherein the dielectric stack comprises a first oxide layer positioned on the surface of the silicon substrate, a nitride block positioned on the surface of the first oxide layer and in the concave structure, and a second oxide layer covering the first oxide layer and the nitride block.
1 . A flash memory structure, comprising:
a semiconductor substrate having at least one concave structure positioned on the surface of the semiconductor substrate;
two doped regions positioned in the semiconductor substrate and at two sides of the concave structure;
at least one carrier trapping region positioned in the concave structure; and
a conductive layer positioned above the concave structure.
2 . The flash memory structure of claim 1 , wherein the concave structure comprises two grooves having a U-shaped or V-shaped profile.
3 . The flash memory structure of claim 2 , wherein the two grooves are separated by a protrusion.
4 . The flash memory structure of claim 1 , wherein the carrier trapping region comprises a dielectric stack positioned in the concave structure.
5 . The flash memory structure of claim 4 , wherein the dielectric stack comprises:
a first oxide layer positioned on the surface of the semiconductor substrate;
a nitride block positioned on the surface of the first oxide layer and in the concave structure; and
a second oxide layer covering the first oxide layer and the nitride block.
6 . The flash memory structure of claim 1 , wherein the semiconductor substrate is a silicon substrate, and the concave structure has an inclined plane with (111) orientation of the silicon substrate.
7 . The flash memory structure of claim 1 , wherein the semiconductor substrate is a silicon substrate, and the concave structure has a bottom plane with (100) orientation of the silicon substrate.
8 . The flash memory structure of claim 1 , wherein the two doped regions are used as a source electrode and a drain electrode.
9 . A method for fabricating a flash memory structure, comprising steps of:
forming two doped regions in a semiconductor substrate;
forming at least one concave structure on the surface of the semiconductor substrate;
forming at least one carrier trapping region in the concave structure; and
forming a conductive layer above the concave structure.
10 . The method for fabricating a flash memory structure of claim 9 , wherein the semiconductor substrate is a silicon substrate, and the step of forming at least one concave structure comprises:
forming a silicon epitaxy layer on the surface of the silicon substrate;
forming a mask layer on the surface of the silicon epitaxy layer;
forming at least one opening in the mask layer; and
performing an etching process to remove a portion of the silicon epitaxy layer below the opening to form the concave structure including at least one groove.
11 . The method for fabricating a flash memory structure of claim 10 , wherein the etching process uses an etchant including potassium hydroxide.
12 . The method for fabricating a flash memory structure of claim 10 , wherein the silicon epitaxy layer has a horizontally positioned crystal plane with (100) orientation.
13 . The method for fabricating a flash memory structure of claim 10 , wherein the groove has an inclined plane with (111) orientation of the silicon epitaxy layer.
14 . The method for fabricating a flash memory structure of claim 10 , wherein the groove has a bottom plane with (100) orientation of the silicon epitaxy layer.
15 . The method for fabricating a flash memory structure of claim 10 , wherein the mask layer is an oxide layer.
16 . The method for fabricating a flash memory structure of claim 10 , wherein the step of forming at least one carrier trapping region comprises:
forming a first oxide layer on the surface of the silicon epitaxy layer;
forming at least one nitride block on the surface of the first oxide layer and in the groove; and
forming a second oxide layer on the surface of the nitride block and on the surface of the first oxide layer.
17 . The method for fabricating a flash memory structure of claim 16 , wherein the step of forming at least one nitride block comprises:
depositing a nitride layer on the first oxide layer;
forming a photoreist layer on the nitride layer;
performing a lithographic process to remove a portion of the photoresist layer above a predetermined depth to form a photoresist mask;
performing an etching process to remove a portion of the nitride layer not covered by the photoresist mask to form the nitride block on the surface of the first oxide layer and in the groove; and
removing the photoresist mask.