Nonvolatile memories and methods of fabrication
In a nonvolatile memory, substrate isolation regions ( 220 ) are formed in a semiconductor substrate ( 120 ). The substrate isolation regions are dielectric regions protruding above the substrate. Then select gate lines ( 140 ) are formed. Then a floating gate layer ( 160 ) is deposited. The floating gate layer is etched until the substrate isolation regions are exposed and the floating layer is removed from over at least a portion of the select gate lines. A dielectric ( 1510 ) is formed over the floating gate layer, and a control gate layer ( 170 ) is deposited. The control gate layer protrudes upward over each select gate line. These protrusions are exploited to define the control gates independently of photolithographic alignment. The floating gates are then defined independently of any photolithographic alignment other than the alignment involved in patterning the substrate isolation regions and the select gate lines. In another aspect, a nonvolatile memory cell has a conductive floating gate ( 160 ). A dielectric layer ( 1510 ) overlying the floating gate has a continuous feature that overlies the floating gate and also overlies the select gate ( 140 ). The control gate ( 160 ) overlies the continuous feature of the dielectric layer and also overlies the floating gate but not the select gate. In another aspect, substrate isolation regions ( 220 ) are formed in a semiconductor substrate. Select gate lines cross over the substrate isolation regions. Each select gate line has a planar top surface, but its bottom surface goes up and down over the substrate isolation regions. Other features are also provided.
1. A method for fabricating an integrated circuit which comprises a nonvolatile memory which comprises an array of nonvolatile memory cells, the integrated circuit comprising an array area containing the array, each memory cell of the array having a conductive floating gate and a first conductive gate insulated from each other, the method comprising:
(a) forming one or more substrate isolation regions in a semiconductor substrate between active areas of the semiconductor substrate, each substrate isolation region being a dielectric region protruding above the semiconductor substrate;
(b) forming one or more conductive lines G 1 , each conductive line G 1 overlying at least one active area, wherein each first conductive gate comprises a portion of a line G 1 ;
(c) forming a layer (“FG layer”) over the first conductive lines and the substrate isolation regions, wherein each floating gate comprises a portion of the FG layer;
(d) partially removing the FG layer to expose the substrate isolation regions and to remove the FG layer from over at least a portion of each conductive line G 1 ;
wherein the FG layer has a planar top surface in the array area at a time before the end of the operation (d); and
the operation (d) comprises partially removing the FG layer after said time without a mask over the array.
2. The method of claim 1 wherein the operation (d) is terminated with reference to a time of detecting that the substrate isolation regions have been exposed.
3. The method of claim 1 wherein each substrate isolation region traverses the memory array, and each conductive line G 1 crosses over plural substrate isolation regions.
4. The method of claim 3 wherein the top surface of each line G 1 is planar but the bottom surface of each line G 1 goes up and down over the substrate isolation regions.
5. The method of claim 1 further comprising, before forming the FG layer, forming a dielectric over a sidewall of each conductive line G 1 to insulate the conductive lines G 1 from the floating gates.
6. The method of claim 5 wherein each memory cell further comprises a second conductive gate insulated from the first conductive gate and the floating gate, and the method further comprises:
(e) after the operation (d), forming a dielectric D 1 over the FG layer;
(f) forming a layer G 2 over the dielectric D 1 , wherein each second conductive gate comprises a portion of the layer G 2 ;
(g) partially removing the layer G 2 and the FG layer to form the floating gates and to form from the layer G 2 one or more conductive lines for the second conductive gates, wherein each second conductive gate comprises a portion of a conductive line formed from the layer G 2 .
7. The method of claim 6 wherein in the operation (f), the layer G 2 is formed to have a portion P 1 protruding above each conductive line G 1 ; and
the operation (g) comprises:
(g1) forming a layer L 1 over the layer G 2 such that the protruding portions P 1 of the layer G 2 are exposed and not completely covered by the layer L 1 ;
(g2) partially removing the layer G 2 selectively to the layer L 1 to form cavities at the locations of the portions P 1 ;
(g3) forming a layer L 2 at least in said cavities; and
(g4) removing at least parts of the layers L 1 and G 2 selectively to the layer L 2 .
8. The method of claim 7 wherein the operation (g1) comprises:
forming the layer L 1 over the entire layer G 2 ; and
planarizing the layer L 1 to expose the protruding portions P 1 .
9. The method of claim 7 wherein the operation (g3) comprises:
forming the layer L 2 over the entire layer L 1 ; and
partially removing the layer L 2 to expose the layer L 1 but leave the layer L 2 in the cavities.
10. The method of claim 7 wherein each line G 1 traverses the array area and crosses over one or more substrate isolation regions, and the method further comprises:
(h) prior to operation (g4), forming a mask over the layer L 2 and removing the layer L 2 through an opening or openings in the mask, so as to remove the layer L 2 on one side of each line G 1 but not on another, opposite side of each line G 1 , the layer L 2 extending on the opposite side of the line G 1 along the line G 1 across the array area.
11. The method of claim 10 wherein:
in the operation (f), the layer G 2 is formed in a peripheral area of the integrated circuit over positions of peripheral transistor gates each of which comprises a portion of the layer G 2 , and the layer G 2 comprises semiconductor material;
in the operation (g1), the layer L 1 is formed over the layer G 2 in the peripheral area;
in the operation (g3), the layer L 2 is formed over the layer G 2 in the peripheral area;
in one or more of the operations (g1), (g3), (g4), and (h), the layers L 1 and L 2 are removed from over the positions of the peripheral transistor gates; and
the method further comprises:
(i) introducing a dopant into an area of at least one peripheral transistor to simultaneously dope the transistor's gate and the transistor's source/drain regions.
12. The method of claim 11 wherein the operation (i) comprises:
introducing an N type dopant into an area of at least one peripheral NMOS transistor to simultaneously dope the NMOS transistor's gate and the NMOS transistor's source/drain regions; and
introducing a P type dopant into an area of at least one peripheral PMOS transistor to simultaneously dope the PMOS transistor's gate and the PMOS transistor's source/drain regions.
13. A method for fabricating an integrated circuit which comprises a nonvolatile memory which comprises an array of nonvolatile memory cells, the integrated circuit comprising an array area containing the array, each memory cell of the array having a first conductive gate, the method comprising:
(i) forming one or more conductive lines G 1 , wherein each first conductive gate comprises a portion of a line G 1 ;
(ii) forming a layer over the first conductive lines, each memory cell having at least one conductive gate comprising a portion of the layer formed in this operation (ii), the layer formed in the operation (ii) having a portion P 1 protruding above each conductive line G 1 ;
(iii) forming a layer L 1 over the layer formed in (ii) such that the protruding portions P 1 of the layer in (ii) are exposed and not completely covered by the layer L 1 ;
(iv) partially removing the layer in (ii) selectively to the layer L 1 to form cavities at the locations of the portions P 1 ;
(v) forming a layer L 2 at least in said cavities; and
(vi) removing at least parts of the layer L 1 and the layer formed in (ii) selectively to the layer L 2 .
14. The method of claim 13 wherein the conductive gate recited in (ii) is a control gate.
15. The method of claim 13 wherein the operation (iii) comprises:
forming the layer L 1 over the entire layer formed in (ii); and
planarizing the layer L 1 to expose the protruding portions P 1 .
16. The method of claim 13 wherein the operation (v) comprises:
forming the layer L 2 over the entire layer L 1 ; and
partially removing the layer L 2 to expose the layer L 1 but leave the layer L 2 in the cavities.
17. The method of claim 13 wherein each line G 1 traverses the array, and the method further comprises:
(vii) prior to operation (vi), forming a mask over the layer L 2 and removing the layer L 2 through an opening or openings in the mask, so as to remove the layer L 2 on one side of each line G 1 but not on another, opposite side of each line G 1 , the layer L 2 extending on the opposite side of the line G 1 along the line G 1 across the array area.
18. The method of claim 17 wherein:
the layer in (ii) is formed in a peripheral area of the integrated circuit over positions of peripheral transistor gates each of which comprises a portion of the layer in (ii), and the layer in (ii) comprises semiconductor material;
in the operation (iii), the layer L 1 is formed over the layer in (ii) in the peripheral area;
in the operation (v), the layer L 2 is formed over the layer in (ii) in the peripheral area;
in one or more of the operations (iii), (v), (vi), and (vii), the layers L 1 and L 2 are removed from over the positions of the peripheral transistor gates; and
the method further comprises:
(viii) introducing a dopant into an area of at least one peripheral transistor to simultaneously dope the transistor's gate and the transistor's source/drain regions.
19. The method of claim 18 wherein the operation (viii) comprises:
introducing an N type dopant into an area of at least one peripheral NMOS transistor to simultaneously dope the NMOS transistor's gate and the NMOS transistor's source/drain regions; and
introducing a P type dopant into an area of at least one peripheral PMOS transistor to simultaneously dope the PMOS transistor's gate and the PMOS transistor's source/drain regions.
20. The method of claim 1 wherein the operation (d) comprises:
(d1) removing a portion of the FG layer in the array area to obtain said planar top surface for the FG layer in the array area.
21. The method of claim 20 wherein the operation (d1) comprises chemical mechanical polishing of the FG layer.
22. The method of claim 1 wherein the FG layer covers the one or more substrate regions at said time.
23. The method of claim 6 wherein at a conclusion of the operation (d) the FG layer covers all of the array except for the conductive lines G 1 and the substrate isolation regions.
24. The method of claim 1 wherein at a conclusion of the operation (d) a top of the FG layer is at most as high as a top of the substrate isolation regions.
25. The method of claim 1 wherein a removal of any portion of the FG layer in the array area through the end of the operation (d) occurs without a mask over the array.
26. A method for fabricating an integrated circuit which comprises a nonvolatile memory which comprises an array of nonvolatile memory cells, the integrated circuit comprising an array area containing the array, each memory cell of the array having a conductive floating gate and a first conductive gate insulated from each other, the method comprising:
(a) forming one or more substrate isolation regions in a semiconductor substrate between active areas of the semiconductor substrate, each substrate isolation region being a dielectric region protruding above the semiconductor substrate;
(b) forming one or more conductive lines G 1 , each conductive line G 1 overlying at least one active area, wherein each first conductive gate comprises a portion of a line G 1 ;
(c) forming a layer (“FG layer”) over the first conductive lines and the substrate isolation regions, wherein each floating gate comprises a portion of the FG layer;
(d) partially removing the FG layer to expose the substrate isolation regions and to remove the FG layer from over at least a portion of each conductive line G 1 ;
wherein the operation (d) comprises partially removing the FG layer without a mask over the array; and
at a conclusion of the partial removing without a mask, a top surface of the FG layer is planar in the array area, and the FG layer covers all of the array except for the conductive lines G 1 and the substrate isolation regions.
27. The method of claim 26 wherein the operation (d) comprises chemical mechanical polishing of the FG layer.
28. The method of claim 27 wherein at a conclusion of chemical mechanical polishing the FG layer covers the one or more substrate isolation regions.
29. The method of claim 26 wherein the operation (d) is terminated with reference to a time of detecting that the substrate isolation regions have been exposed.
30. The method of claim 26 wherein each substrate isolation region traverses the memory array, and each conductive line G 1 crosses over plural substrate isolation regions.
31. The method of claim 30 wherein the top surface of each line G 1 is planar but the bottom surface of each line G 1 goes up and down over the substrate isolation regions.
32. The method of claim 26 further comprising, before forming the FG layer, forming a dielectric over a sidewall of each conductive line G 1 to insulate the conductive lines G 1 from the floating gates.
33. The method of claim 32 wherein each memory cell further comprises a second conductive gate insulated from the first conductive gate and the floating gate, and the method further comprises:
(e) after the operation (d), forming a dielectric D 1 over the FG layer;
(f) forming a layer G 2 over the dielectric D 1 , wherein each second conductive gate comprises a portion of the layer G 2 ;
(g) partially removing the layer G 2 and the FG layer to form the floating gates and to form from the layer G 2 one or more conductive lines for the second conductive gates, wherein each second conductive gate comprises a portion of a conductive line formed from the layer G 2 .
34. The method of claim 33 wherein in the operation (f), the layer G 2 is formed to have a portion P 1 protruding above each conductive line G 1 ; and
the operation (g) comprises:
(g1) forming a layer L 1 over the layer G 2 such that the protruding portions P 1 of the layer G 2 are exposed and not completely covered by the layer L 1 ;
(g2) partially removing the layer G 2 selectively to the layer L 1 to form cavities at the locations of the portions P 1 ;
(g3) forming a layer L 2 at least in said cavities; and
(g4) removing at least parts of the layers L 1 and G 2 selectively to the layer L 2 .
35. The method of claim 34 wherein the operation (g1) comprises:
forming the layer L 1 over the entire layer G 2 ; and
planarizing the layer L 1 to expose the protruding portions P 1 .
36. The method of claim 34 wherein the operation (g3) comprises:
forming the layer L 2 over the entire layer L 1 ; and
partially removing the layer L 2 to expose the layer L 1 but leave the layer L 2 in the cavities.
37. The method of claim 34 wherein each line G 1 traverses the array area and crosses over one or more substrate isolation regions, and the method further comprises:
(h) prior to operation (g4), forming a mask over the layer L 2 and removing the layer L 2 through an opening or openings in the mask, so as to remove the layer L 2 on one side of each line G 1 but not on another, opposite side of each line G 1 , the layer L 2 extending on the opposite side of the line G 1 along the line G 1 across the array area.
38. The method of claim 37 wherein:
in the operation (f), the layer G 2 is formed in a peripheral area of the integrated circuit over positions of peripheral transistor gates each of which comprises a portion of the layer G 2 , and the layer G 2 comprises semiconductor material;
in the operation (g1), the layer L 1 is formed over the layer G 2 in the peripheral area;
in the operation (g3), the layer L 2 is formed over the layer G 2 in the peripheral area;
in one or more of the operations (g1), (g3), (g4), and (h), the layers L 1 and L 2 are removed from over the positions of the peripheral transistor gates; and
the method further comprises:
(i) introducing a dopant into an area of at least one peripheral transistor to simultaneously dope the transistor's gate and the transistor's source/drain regions.
39. The method of claim 38 wherein the operation (i) comprises:
introducing an N type dopant into an area of at least one peripheral NMOS transistor to simultaneously dope the NMOS transistor's gate and the NMOS transistor's source/drain regions; and
introducing a P type dopant into an area of at least one peripheral PMOS transistor to simultaneously dope the PMOS transistor's gate and the PMOS transistor's source/drain regions.
40. A method for fabricating an integrated circuit which comprises a nonvolatile memory which comprises an array of nonvolatile memory cells, the integrated circuit comprising an array area containing the array, each memory cell of the array having a conductive floating gate and a first conductive gate insulated from each other, the method comprising:
(a) forming one or more substrate isolation regions in a semiconductor substrate between active areas of the semiconductor substrate, each substrate isolation region being a dielectric region protruding above the semiconductor substrate;
(b) forming one or more conductive lines G 1 , each conductive line G 1 overlying at least one active area, wherein each first conductive gate comprises a portion of a line G 1 ;
(c) forming a layer (“FG layer”) over the first conductive lines and the substrate isolation regions, wherein each floating gate comprises a portion of the FG layer;
(d) partially removing the FG layer to expose the substrate isolation regions and to remove the FG layer from over at least a portion of each conductive line G 1 ;
wherein the method further comprises, before forming the FG layer, forming a dielectric over a sidewall of each conductive line G 1 to insulate the conductive lines G 1 from the floating gates;
wherein each memory cell further comprises a second conductive gate insulated from the first conductive gate and the floating gate, and the method further comprises:
(e) after the operation (d), forming a dielectric D 1 over the FG layer;
(f) forming a layer G 2 over the dielectric D 1 , wherein each second conductive gate comprises a portion of the layer G 2 ;
(g) partially removing the layer G 2 and the FG layer to form the floating gates and to form from the layer G 2 one or more conductive lines for the second conductive gates, wherein each second conductive gate comprises a portion of a conductive line formed from the layer G 2 .
41. The method of claim 40 wherein in the operation (f), the layer G 2 is formed to have a portion P 1 protruding above each conductive line G 1 ; and
the operation (g) comprises:
(g1) forming a layer L 1 over the layer G 2 such that the protruding portions P 1 of the layer G 2 are exposed and not completely covered by the layer L 1 ;
(g2) partially removing the layer G 2 selectively to the layer L 1 to form cavities at the locations of the portions P 1 ;
(g3) forming a layer L 2 at least in said cavities; and
(g4) removing at least parts of the layers L 1 and G 2 selectively to the layer L 2 .
42. The method of claim 41 wherein the operation (g1) comprises:
forming the layer L 1 over the entire layer G 2 ; and
planarizing the layer L 1 to expose the protruding portions P 1 .
43. The method of claim 41 wherein the operation (g3) comprises:
forming the layer L 2 over the entire layer L 1 ; and
partially removing the layer L 2 to expose the layer L 1 but leave the layer L 2 in the cavities.
44. The method of claim 41 wherein each line G 1 traverses the array area and crosses over one or more substrate isolation regions, and the method further comprises:
(h) prior to operation (g4), forming a mask over the layer L 2 and removing the layer L 2 through an opening or openings in the mask, so as to remove the layer L 2 on one side of each line G 1 but not on another, opposite side of each line G 1 , the layer L 2 extending on the opposite side of the line G 1 along the line G 1 across the array area.
45. The method of claim 44 wherein:
in the operation (f), the layer G 2 is formed in a peripheral area of the integrated circuit over positions of peripheral transistor gates each of which comprises a portion of the layer G 2 , and the layer G 2 comprises semiconductor material;
in the operation (g1), the layer L 1 is formed over the layer G 2 in the peripheral area;
in the operation (g3), the layer L 2 is formed over the layer G 2 in the peripheral area;
in one or more of the operations (g1), (g3), (g4), and (h), the layers L 1 and L 2 are removed from over the positions of the peripheral transistor gates; and
the method further comprises:
(i) introducing a dopant into an area of at least one peripheral transistor to simultaneously dope the transistor's gate and the transistor's source/drain regions.
46. The method of claim 45 wherein the operation (i) comprises:
introducing an N type dopant into an area of at least one peripheral NMOS transistor to simultaneously dope the NMOS transistor's gate and the NMOS transistor's source/drain regions; and
introducing a P type dopant into an area of at least one peripheral PMOS transistor to simultaneously dope the PMOS transistor's gate and the PMOS transistor's source/drain regions.