Method of forming two-transistor pixel with buried reset channel
View Patent ↗A two-transistor pixel of an imager has a reset region formed adjacent a charge collection region of a photodiode and in electrical communication with a gate of a source follower transistor. The reset region is connected to one terminal of a capacitor which integrates collected charge of the photodiode. The charge collection region is reset by pulsing the other terminal of the capacitor from a higher to a lower voltage.
1. A method of forming a pixel, said method comprising:
forming a layer of a first conductivity type over a substrate;
forming a charge collection region of a second conductivity type below a surface of said layer; and
forming a reset region of said second conductivity type in said layer in contact with said charge collection region, said reset region forming with said charge collection region an extended charge collection region, said reset region being operable to apply a reset signal to said extended charge collection region.
2. The method of claim 1 wherein said reset region is formed by implanting a dopant of said second conductivity type within said layer and adjacent said charge collection region.
3. The method of claim 2 wherein said reset region is doped with an n-type dopant at a first dopant concentration.
4. The method of claim 3 further comprising forming a capacitor for storing charge collected in said extended charge collection region, said capacitor having one terminal in electrical communication with said reset region and with a source follower transistor through a contact region.
5. The method of claim 4 wherein said contact region is doped with an n-type dopant at a second dopant concentration which is higher than said first dopant concentration.
6. The method of claim 4 wherein said capacitor has a charge-per-unit area capacitance of about 5 to about 10 fF/μm 2 .
7. A method of forming a pixel, said method comprising:
forming a layer of a first conductivity type over a substrate;
forming a charge collection region of a second conductivity type below a surface of said layer;
forming a reset region of said second conductivity type in said layer in contact with said charge collection region, said reset region forming with said charge collection region an extended charge collection region, said reset region being operable to apply a reset signal to said extended charge collection region;
forming a source follower transistor for outputting a signal representing charge collected in said charge collection region; and
forming a capacitor for storing charge collected in said extended charge collection region, said capacitor having one terminal in electrical communication with said reset region and said source follower transistor.
8. The method of claim 7 wherein said reset region is formed by implanting a dopant of said second conductivity type within said layer and adjacent said charge collection region.
9. The method of claim 8 wherein said reset region is doped with an n-type dopant at a first dopant concentration.
10. The method of claim 7 wherein said capacitor is in electrical communication with said reset region through a contact region.
11. The method of claim 10 wherein said contact region is doped with an n-type dopant at a second dopant concentration which is higher than said first dopant concentration.
12. The method of claim 7 wherein said first conductivity type is p-type and said second conductivity type is n-type.
13. The method of claim 7 wherein said capacitor has a charge-per-unit area capacitance of about 5 to about 10 fF/μm 2 .
14. A method of forming a two-transistor pixel, said method comprising:
forming a charge collection region of a first conductivity type below a surface of a substrate;
forming a reset region of said first conductivity type below said surface of said substrate, said reset region being in contact with said charge collection region and laterally displaced from said charge collection region, said reset region forming with said charge collection region an extended charge collection region;
forming a contact region of a second conductivity type below said surface of said substrate and within said reset region;
forming a source follower transistor for outputting a signal representing charge collected in said extended charge collection region; and
forming a row select transistor for selectively outputting a signal from said source follower transistor.
15. The method of claim 14 further comprising forming a capacitor for storing charge collected in said extended charge collection region, said capacitor having one terminal in electrical communication with said reset region and said source follower transistor.
16. The method of claim 15 wherein said capacitor has a charge-per-unit area capacitance of about 5 to about 10 fF/μm 2 .
17. The method of claim 14 further comprising providing a pulsed voltage source for causing said reset region to periodically reset said reset region and said extended charge collection region.
18. The method of claim 14 wherein said reset region is doped with a dopant at a first dopant concentration and said charge collection region is doped with said dopant at a second dopant concentration.
19. The method of claim 18 wherein said first dopant concentration is greater than said second dopant concentration.