Granted Patent B2

US 6,903,367 · App. 10/637,727 · Granted Jun 7, 2005

Abstract

Claims (110)

1. A decoder for a memory device, comprising:

a number of address lines;

a number of output lines;

wherein the address lines, and the output lines form an array;

a number of vertical pillars extending outwardly from a semiconductor substrate at intersections of output lines and address lines, wherein each pillar includes a single crystalline first contact layer and a second contact layer separated by an oxide layer;

a number of vertical floating gate transistors, each floating gate transistor being formed in a single crystalline layer that is selectively disposed on a side of one of the vertical pillars, the single crystalline layer having a thickness of less than 10 nanometers from the side of the vertical pillar and extending in a direction normal to the side of the vertical pillar, wherein each transistor includes:

a first source/drain region in contact with the first contact layer;

a second source/drain region in contact with the second contact layer;

a body region which opposes the oxide layer and contacts the first and the second source/drain regions; and

a floating gate opposing the body region;

a plurality of buried source lines formed of single crystalline semiconductor material and disposed below the pillars in the array for interconnecting with the first contact layer of pillars in the array; and

wherein each of the number of address lines is disposed between rows of the pillars and opposes the floating gates of the vertical floating gate transistors and serves as a control gate.

2. The decoder of claim 1 , wherein the number of address lines includes a number of complementary address lines that are disposed in the array which serve as control gates for the number of vertical floating gate transistors selectively disposed alongside of pillars at intersections of the complementary address lines with the output lines.

3. The decoder of claim 1 , wherein the number of vertical floating gate transistors are each formed in a single crystalline layer on one side of the number of vertical pillars with one of the address lines forming a control gate adjacent to the floating gates of the vertical floating gate transistors along a row of pillars, and wherein each output line is coupled to the second contact layer along a column of pillars.

4. The decoder of claim 1 , wherein a vertical floating gate transistor is formed in a single crystalline layer on two opposing sides of each pillar.

5. The decoder of claim 1 , wherein in a column adjacent pair of pillars an address line is formed in a trench between the column adjacent pair of pillars, the address line forming a control gate for a pair of floating gates in the column adjacent pair, and wherein each output line is coupled to the second contact layer in the column adjacent pair of pillars.

6. The decoder of claim 1 , wherein at least one of the output lines includes a redundant wordline.

7. The decoder of claim 1 , wherein the semiconductor substrate includes a silicon on insulator substrate.

8. The decoder of claim 1 , wherein the body region is formed from solid phase epitaxial growth.

9. The decoder of claim 1 , wherein the plurality of buried source lines are more heavily doped than the first contact layer and are formed integrally with the first contact layer.

10. A decoder for a memory device, comprising:

a number of address lines;

a number of output lines;

wherein the address lines, and the output lines form an array;

a number of vertical pillars extending outwardly from a semiconductor substrate at intersections of output lines and address lines, wherein each pillar includes a single crystalline first contact layer and a second contact layer separated by an oxide layer;

a number of single crystalline layers that are disposed along a side of the number of vertical pillars, wherein each single crystalline layer includes:

a first source/drain region coupled to the first contact layer;

a second source/drain region coupled to the second contact layer; and

a body region which opposes the oxide layer and couples the first and the second source/drain regions;

wherein a horizontal junction depth for the first and the second source/drain regions is less than 10 nanometers and the body region includes a channel having a thickness less than 10 nanometers and a vertical channel length less than 100 nanometers;

a floating gate opposing the body region and separated therefrom by a gate oxide;

a plurality of buried source lines formed of single crystalline semiconductor material and disposed below the pillars in the array for interconnecting with the first contact layer of pillars in the array; and

wherein each of the number of address lines is disposed between rows of the pillars and opposes the floating gates of the vertical floating gate transistors for serving as a control gate.

11. The decoder of claim 10 , wherein the single crystalline layer has a thickness of less than 10 nanometers extending away from and normal to the surface of the pillar.

12. A programmable decode circuit for a semiconductor memory, comprising:

a number of address lines;

a number of output lines;

wherein the address lines, and the output lines form an array;

a number of vertical pillars extending outwardly from a semiconductor substrate at intersections of output lines and address lines, wherein each pillar includes a single crystalline first contact layer and a second contact layer separated by an oxide layer;

a pair of vertical floating gate transistors formed in a pair of single crystalline layers along opposing sides of each pillar, wherein each single crystalline layer has a thickness of less than 10 nanometers extending away from and normal to the side of the pillar, and each vertical floating gate transistor includes:

a first source/drain region found in the single crystalline layer and coupled to the first contact layer;

a second source/drain region found in the single crystalline layer and coupled to the second contact layer;

a body region found in the single crystalline layer, the body region connecting the first and the second source/drain regions;

wherein a surface space charge region for the vertical transistor scales down as other dimensions of the transistor scale down; and

a floating gate opposing the body region and separated therefrom by a gate oxide, and wherein the floating gate is formed in a trench between rows of the number of pillars and is shared between the vertical floating gate transistors that are adjacent the trench in column adjacent pillars;

a plurality of buried source lines formed of single crystalline semiconductor material and disposed below the pillars in the array for interconnecting with the first contact layer of pillars in the array; and

wherein each of the number of address lines is disposed between rows of the pillars and opposes the floating gates of the vertical floating gate transistors for serving as a control gate.

13. The programmable decode circuit of claim 14 , wherein each address line integrally forms a control gate for addressing floating gates in the trench and is isolated from the floating gates by an insulator layer.

14. The programmable decode circuit of claim 12 , wherein each body region includes a p-type channel having a vertical length of less than 100 nanometers.

15. The programmable decode circuit of claim 12 , wherein the number of buried source lines are formed integrally with the first contact layer and are separated from the semiconductor substrate by an oxide layer.

16. The programmable decode circuit of claim 12 , wherein each address line includes a horizontally-oriented control line having a vertical side length of less than 100 nanometers.

17. A decoder, comprising:

a number of vertical pillars extending outwardly from a substrate;

a number of vertically-oriented single crystalline layers, each layer being selectively disposed on a side of one of the vertical pillars, each single crystalline layer having a thickness of less than 10 nanometers extending from and in a direction normal to the side of the vertical pillar;

each single crystalline layer including a first source/drain region and a second source/drain region separated by a body region;

a floating gate positioned adjacent to the body region and separated from the body region by a floating gate dielectric;

a number of address lines, each address line being formed adjacent to and separated from a number of the floating gates by a control gate dielectric; and

a number of data lines, each data line being electrically connected to one of the first and second source/drain regions for a number of the single crystalline layers,

wherein a logic function is implemented to select one of the data lines as a function of an address provided on the address lines and a charge stored on the floating gates.

18. A decoder, comprising:

a number of vertical pillars extending outwardly from a substrate, each pillar including a single crystalline first contact layer and a second contact layer separated by an oxide layer;

a number of vertically-oriented single crystalline layers, each layer being selectively disposed on a side of one of the vertical pillars, each single crystalline layer having a vertical length of less than 100 nanometers and a thickness of less than 10 nanometers extending from and in a direction normal to the side of the vertical pillar;

each single crystalline layer including a first source/drain region and a second source/drain region separated by a body region, wherein the first source/drain region is in contact with the first contact layer of the pillar, the body region is in contact with the oxide of the pillar, and the second source/drain region is in contact with the second contact layer of the pillar;

a floating gate positioned adjacent to the body region and separated from the body region by a floating gate dielectric;

a number of address lines, each address line being formed adjacent to and separated from a number of the floating gates by a control gate dielectric; and

a number of data lines, each data line being connected to the first contact layer for a number of the pillars,

wherein a logic function is implemented to select one of the data lines as a function of an address provided on the address lines and a charge stored on the floating gates.

19. A decode circuit for a semiconductor memory, comprising:

a number of address lines;

a number of output lines;

wherein the address lines, and the output lines form an array;

a number of vertical pillars extending outwardly from a semiconductor substrate at intersections of output lines and address lines, wherein each pillar includes a single crystalline first contact layer and a second contact layer separated by an oxide layer;

a pair of vertical floating gate transistors formed on opposing sides of each pillar, wherein each single crystalline vertical floating gate transistor includes;

a first source/drain region coupled to the first contact layer;

a second source/drain region coupled to the second contact layer;

a body region which opposes the oxide layer and couples the first and the second source/drain regions; and

a floating gate opposing the body region in a trench and separated therefrom by a tunnel oxide; and

wherein each of the number of address lines is disposed between rows of the pillars and is shared as a control gate for addressing floating gates on opposing sides of the trench in column adjacent pillars.

20. The decode circuit of claim 19 , wherein each of the number of address lines is located in the trench between the floating gates on opposing sides of the trench in column adjacent pillars, and wherein each of the number of address lines includes a vertically oriented address line having a vertical length of less than 100 nanometers.

21. The decode circuit of claim 19 , wherein each vertical floating gate transistor has a vertical length of less than 100 nanometers and a horizontal width of less than 10 nanometers.

22. An address decode circuit, comprising:

a number of address lines;

a number of data lines that are selectively coupled to the address lines;

wherein the address lines and the data lines form an array; and

a number of vertical floating gate transistors that are selectively disposed at intersections of data lines and address lines, wherein each vertical floating gate transistor includes:

a vertical pillar and a vertical crystalline layer on a side of the pillar, the vertical crystalline layer having a vertical length less than 100 nanometers and a thickness less than 10 nanometers extending away from and normal to the side of the pillar;

a first source/drain region in the vertical crystalline layer;

a second source/drain region in the vertical crystalline layer;

a body region in the vertical crystalline layer which contacts the first and the second source/drain regions; and

a floating gate separated from the body region by a gate oxide;

wherein each of the number of data lines is coupled to the second source/drain region in column adjacent pillars; and

wherein the number of address lines integrally form control lines opposing the floating gates of the vertical floating gate transistors such that the vertical floating gate transistors implement a logic function that selects a data line responsive to an address provided to the address lines and a charge stored on the floating gates.

23. The address decode circuit of claim 22 , wherein each of the address lines includes a vertically oriented address line having a vertical length of less than 100 nanometers and formed in a trench between floating gates.

24. The address decode circuit of claim 22 , wherein each of the address lines includes a horizontally oriented address line located above the floating gates for row adjacent vertical floating gate transistors.

25. A memory device, comprising:

an array of wordlines and complementary bit line pairs;

a number of memory cells that are each addressably coupled at intersections of a word line with a bit line of a complementary bit line pair;

a row decoder that is coupled to the wordlines so as to implement a logic function that selects one of the wordlines responsive to an address provided to the row decoder on a number of first address lines;

a number of sense amplifiers, each coupled to a complementary pair of bit lines;

a column decoder that is coupled to the sense amplifiers so as to implement a logic function that selects one of the complementary pairs of bit lines responsive to an address provided to the column decoder on a number of second address lines; and

wherein each of the row decoder and the column decoder comprise an array of vertical floating gate transistors that are selectively coupled to implement a logic function that selects a wordline based on addresses supplied on the number of first address lines, wherein each vertical floating gate transistor includes:

a vertically-oriented single crystalline layer having a thickness of less than 10 nanometers;

a first source/drain region formed in the single crystalline layer to have a junction depth less than 10 nanometers;

a second source/drain region formed in the single crystalline layer to have a junction depth less than 10 nanometers;

a body region in the single crystalline layer between the first and the second source/drain regions; and

a floating gate opposing the body region and separated therefrom by a gate oxide.

26. The memory device of claim 25 , wherein each of the first address lines are formed in a trench opposing the floating gates, and wherein each of the first address lines include vertically oriented address lines having a vertical length of less than 100 nanometers.

27. The memory device of claim 25 , wherein each of the first address lines include horizontally oriented address lines formed above the floating gates.

28. The memory device of claim 25 , wherein each of the wordlines couples to the second source/drain region of the vertical floating gate transistors in the row decoder.

29. The memory device of claim 25 , wherein each vertical floating gate transistor has a vertical length of less than 100 nanometers.

Assignments (8)