Leakage current reduction for CMOS memory circuits
A CMOS integrated circuit (e.g., an SRAM or a DRAM) is partitioned into a core block, a peripheral block, and a retention block. The core block includes circuits (e.g., memory cells) that are powered on at all times and is coupled directly to power supply and circuit ground. The peripheral block includes circuits that may be powered on or off and are coupled to the power supply via a head switch and/or to circuit ground via a foot switch. The switches and the core block may be implemented with high threshold voltage (high-Vt) FET devices to reduce leakage current. The peripheral block may be implemented with low-Vt FET devices for high-speed operation. The retention block includes circuits (e.g., pull-up devices) that maintain signal lines (e.g., word lines) at a predetermined level so that the internal states of the core block are retained when the peripheral block is powered off.
1. An integrated circuit comprising:
a core block comprised of a plurality of high threshold voltage (high-Vt) field effect transistor (FET) devices;
a peripheral block comprised of a plurality of low threshold voltage (low-Vt) FET devices;
at least one switch coupled to the peripheral block and operable to power on or off the peripheral block, and
a retention block comprised of at least one FET device operable to maintain at least one control signal at a predetermined level when the peripheral block is powered off.
2. The integrated circuit of claim 1 , wherein the peripheral block is powered on in an operational mode and powered off in a standby mode.
3. The integrated circuit of claim 1 , wherein the core block includes memory cells and the peripheral block includes support circuitry for the memory cells.
4. The integrated circuit of claim 1 , wherein the core block is directly coupled to a power supply and circuit ground.
5. The integrated circuit of claim 1 , wherein the at least one switch includes a head switch coupled between a power supply and the peripheral block.
6. The integrated circuit of claim 5 , wherein the at least one switch further includes a foot switch coupled between the peripheral block and circuit ground.
7. A memory unit comprising:
a core block comprised of a plurality of high threshold voltage (high-Vt) field effect transistor (FET) devices configured to implement memory cells;
a peripheral block comprised of a plurality of low threshold voltage (low-Vt) FET devices configured to implement support circuitry for the memory cells;
at least one switch coupled to the peripheral block and operable to power on or off the peripheral block, and
a retention block operable to maintain a set of control signals at a predetermined level when the peripheral block is powered off.
8. The memory unit of claim 7 , wherein the memory unit is implemented as static random access memory (SRAM).
9. The memory unit of claim 7 , wherein the memory unit is implemented as dynamic random access memory (DRAM).
10. The memory unit of claim 8 , wherein the retention block comprises a plurality of pull-up FET devices operable to maintain the set of control signals at the predetermined level to retain data within the memory cells.
11. The memory unit of claim 8 , wherein the set of control signals is a set of word lines for the memory cells and is maintained at logic low when the peripheral block is powered off.
12. The memory unit of claim 7 , wherein the at least one switch includes
a head switch coupled between a power supply and the peripheral block, and
a foot switch coupled between the peripheral block and circuit ground.
13. The memory unit of claim 7 , wherein the memory cells are dual-bank memory cells.
14. The memory unit of claim 7 , wherein the peripheral block includes word line drivers for the memory cells in the core block.
15. A memory unit comprising:
a core block comprised of a plurality of high threshold voltage (high-Vt) field effect transistor (FET) devices configured to implement memory cells;
a peripheral block comprised of a plurality of low threshold voltage (low-Vt) FET devices configured to implement support circuitry for the memory cells;
at least one switch coupled to the peripheral block and operable to power on or off the peripheral block,
wherein a clock signal for the peripheral block is disabed Tpd seconds prior to powering down the peripheral block and is enabled Tup seconds after powering up the peripheral block, where Tpd and Tup each denotes a non-zero time period.
16. A wireless device comprising an integrated circuit having
a core block comprised of a plurality of high threshold voltage (high-Vt) field effect transistor (FET) devices;
a peripheral block comprised of a plurality of low threshold voltage (low-Vt) FET devices;
at least one switch coupled to the peripheral block and operable to power on or off the peripheral block, and
a retention block operable to maintain at least one control signal at a predetermined level.
17. The wireless device of claim 16 , wherein the integrated circuit implements a static random access memory (SRAM).
18. The wireless device of claim 16 , wherein the integrated circuit implements a digital signal processor (DSP).
19. The wireless device of claim 16 , wherein the integrated circuit implements a controller.
20. The wireless device of claim 16 , wherein said device is operable in a code division multiple access (CDMA) communication system.
21. An apparatus comprising:
a core block comprised of a plurality of high threshold voltage (high-Vt) field effect transistor (FET) devices;
a peripheral block comprised of a plurality of low threshold voltage (low-Vt) FET devices;
means for powering on and off the peripheral block; and
retention means for maintaining a set of control signals at a predetermined level when the peripheral block is powered off.