IP Library Granted Patent US 6,944,250
Granted Patent B2
US 6,944,250 · App. 10/646,971 · Granted Sep 13, 2005

Variable rate modulator

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Quick Facts
Patent No.
US 6,944,250
App. No.
10/646,971
Granted
Sep 13, 2005
Kind
B2
Abstract

Digital data signals at a variable input frequency are converted by a numerically controlled oscillator and an interpolator to a signal at a fixed output sampling frequency. The conversion of the variable input frequency to the fixed output sampling frequency may be by a factor other than an integer. The interpolated digital data signals at the fixed output sampling frequency are then modulated into a pair of trigonometric signals at a programmable carrier frequency, one signal having a cosine function and the other signal having a sine function. The modulated signals at the fixed output sampling frequency are then combined to create a modulated signal at a carrier frequency determined by the frequency of the sine and cosine signals. The modulated signal is sampled at the fixed output sampling frequency and converted to a corresponding analog signal using a digital-to-analog converter.

Claims (25)

1. A signal processing system for converting a variable frequency input signal to a fixed frequency output signal comprising:

means for generating a first clock signal at a first clock frequency;

means for receiving a frequency control signal that corresponds to a second frequency;

means for generating a second clock signal at the second frequency as a function of said frequency control signal;

means for generating a phase offset signal representing an offset in phase between the first clock signal and the second clock signal; and

means for converting the variable frequency input signal to an interpolated signal at a fixed sampling frequency in accordance with said phase offset signal, wherein the interpolated signal is interpolated by a value of M/N where M and N are integers.

2. The signal processing system of claim 1 further comprising:

means for modulating the interpolated signal onto trigonometric signals; and

means for converting the modulated signal to an analog signal.

3. The signal processing system of claim 1 wherein the means for converting a variable frequency input signal to an interpolated signal at a fixed sampling frequency in accordance with said phase offset signal comprises an interpolator that interpolates the variable frequency input signal by a non-integer value.

4. The signal processing system of claim 1 wherein the means for converting a variable frequency input signal to an interpolated signal at a fixed sampling frequency in accordance with said phase offset signal comprises an interpolator that interpolates the variable frequency input signal by an integer value.

5. A signal processing system for converting a variable frequency input signal to an output signal having a fixed output frequency, comprising:

means for generating a clock signal at a clock frequency equal to baud rate of said variable frequency input signal as a function of a frequency control signal;

means for generating a phase offset signal representing an offset in phase between a recipient clock signal and the clock signal; and

means for converting the variable frequency input signal to an interpolated signal at a fixed sampling frequency in accordance with said phase offset signal, wherein the interpolated signal is interpolated by a value of M/N where N and N are integers.

6. A signal processing system, comprising:

means for providing a first clock signal at a first clock frequency;

oscillator means, responsive to a frequency control signal and the first clock signal for providing an output clock signal at a fixed second clock frequency and a phase offset signal representing an offset in phase between the first clock signal and the second clock signal, and

interpolation means for offsetting a pair of variable frequency input signals in accordance with the phase offset signal to provide an interpolated signal at a fixed output sampling frequency, wherein the interpolated signal is interpolated by a value of M/N where M and N are integers.

7. The signal processing system of claim 6 wherein the phase offset signal is greater than or equal to zero and less than one.

8. The signal processing system of claim 6 wherein the interpolation means interpolates the variable frequency input signal by a non-integer value.

9. The signal processing system of claim 6 wherein the interpolation means interpolates the variable frequency input signal by an integer value.

10. The signal processing system of claim 6 further comprising a modulator for modulating the interpolated signal onto a trigonometric signal at a carrier frequency.

11. The signal processing system of claim 10 further comprising a digital to analog converter for converting the modulated signal to an analog signal.

12. The signal processing system of claim 6 wherein said interpolation means includes a register, responsive to said second clock signal, to provide said pair of variable frequency input signals.

Assignments (5)
CORRECTIVE ASSIGNMENT TO CORRECT THE EXECUTION DATE PREVIOUSLY RECORDED AT REEL: 047196 FRAME: 0097. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Mar 6, 2019
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 048555/0510 →
MERGER Recorded Oct 4, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047196/0097 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: BROADCOM CORPORATION
Reel/Frame 041712/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 1, 2017
From: BROADCOM CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041706/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: BROADCOM CORPORATION
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037806/0001 →