IP Library Granted Patent US 6,992,396
Granted Patent B2
US 6,992,396 · App. 10/649,741 · Granted Jan 31, 2006

Semiconductor device and method for fabricating the same

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Quick Facts
Patent No.
US 6,992,396
App. No.
10/649,741
Granted
Jan 31, 2006
Kind
B2
Abstract

A semiconductor device has a substrate having electrode pads, a first semiconductor chip mounted on the substrate with a first adhesion layer interposed therebetween, a second semiconductor chip mounted on the first semiconductor chip with a second adhesion layer interposed therebetween and having electrode pads on the upper surface thereof, wires for bonding the electrode pads of the substrate and the electrode pads of the second semiconductor chip to each other, and a mold resin sealing therein the first and second semiconductor chips and the wires. The peripheral edge portion of the first adhesion layer is protruding outwardly from the first semiconductor chip and the peripheral edge portion of the second semiconductor chip is protruding outwardly beyond the peripheral edge portion of the first semiconductor chip.

Claims (21)

1. A semiconductor device comprising:

a substrate having an electrode pad;

a first semiconductor chip mounted on the substrate with a first adhesion layer interposed therebetween;

a second semiconductor chip mounted on the first semiconductor chip with a second adhesion layer interposed therebetween and having an electrode pad on an upper surface thereof;

a wire for bonding the electrode pad of the substrate and the electrode pad of the second semiconductor chip to each other; and

a mold resin sealing therein the first and second semiconductor chips and the wire,

the first adhesion layer having a peripheral edge portion protruding outwardly from the first semiconductor chip,

the second semiconductor chip having a peripheral edge portion protruding outwardly beyond the outermost part of the peripheral edge portion of the first adhesion layer.

2. A semiconductor device comprising:

a substrate having an electrode pad;

a first semiconductor chip mounted on the substrate with a first adhesion layer interposed therebetween;

a second semiconductor chip mounted on the first semiconductor chip with a second adhesion layer interposed therebetween and having an electrode pad on an upper surface thereof;

a wire for bonding the electrode pad of the substrate and the electrode pad of the second semiconductor chip to each other; and

a mold resin sealing therein the first and second semiconductor chips and the wire,

the first adhesion layer having a peripheral edge portion protruding outwardly from the first semiconductor chip,

the second semiconductor chip having a peripheral edge portion protruding outwardly beyond the peripheral edge portion of the first adhesion layer,

wherein a center of the second semiconductor chip is offset from a center of the first semiconductor chip.

3. The semiconductor device of claim 2 , wherein the center of the second semiconductor chip is offset from the center of the first semiconductor chip in a direction of an edge of the peripheral edge portion of the first adhesion layer which is protruding most outwardly from the first semiconductor chip.

4. The semiconductor device of claim 2 , wherein the center of the second semiconductor chip is offset from the center of the first semiconductor chip in a direction of an edge of the peripheral edge portion of the first adhesion layer which has a largest surface height from the substrate.

5. The semiconductor device of claim 2 , wherein the center of the second semiconductor chip substantially coincides with a center of the substrate.

6. The semiconductor device of claim 1 , wherein the second adhesion layer has a film-like configuration.

Assignments (7)
RELEASE OF SECURITY INTEREST Recorded Jun 11, 2020
From: ROYAL BANK OF CANADA
To: TESSERA, INC.; INVENSAS BONDING TECHNOLOGIES, INC. (F/K/A ZIPTRONIX, INC.); FOTONATION CORPORATION (F/K/A DIGITALOPTICS CORPORATION AND F/K/A DIGITALOPTICS CORPORATION MEMS); INVENSAS CORPORATION; TESSERA ADVANCED TECHNOLOGIES, INC; DTS, INC.; DTS LLC; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
Reel/Frame 052920/0001 →
SECURITY INTEREST Recorded Jun 1, 2020
From: ROVI SOLUTIONS CORPORATION; ROVI TECHNOLOGIES CORPORATION; ROVI GUIDES, INC.; TIVO SOLUTIONS INC.; VEVEO, INC.; INVENSAS CORPORATION; INVENSAS BONDING TECHNOLOGIES, INC.; TESSERA, INC.; TESSERA ADVANCED TECHNOLOGIES, INC.; DTS, INC.; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
To: BANK OF AMERICA, N.A.
Reel/Frame 053468/0001 →
SECURITY INTEREST Recorded Dec 2, 2016
From: INVENSAS CORPORATION; TESSERA, INC.; TESSERA ADVANCED TECHNOLOGIES, INC.; ZIPTRONIX, INC.; DIGITALOPTICS CORPORATION; DIGITALOPTICS CORPORATION MEMS; DTS, LLC; DTS, INC.; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
To: ROYAL BANK OF CANADA, AS COLLATERAL AGENT
Reel/Frame 040797/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 25, 2016
From: PANNOVA SEMIC, LLC
To: TESSERA ADVANCED TECHNOLOGIES, INC.
Reel/Frame 037581/0466 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 7, 2015
From: PANASONIC CORPORATION
To: PANNOVA SEMIC, LLC
Reel/Frame 036065/0273 →
CHANGE OF NAME Recorded Nov 20, 2008
From: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
To: PANASONIC CORPORATION
Reel/Frame 021930/0876 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 28, 2003
From: ARAI, YOSHIYUKI; YUI, TAKASHI; TAKEOKA, YOSHIAKI; ITOU, FUMITO; YAGUCHI, YASUTAKE
To: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
Reel/Frame 014442/0455 →