IP Library › Granted Patent US 7,075,169
Granted Patent B2
US 7,075,169 · App. 10/654,030 · Granted Jul 11, 2006

Semiconductor device having a hollow region and method of manufacturing the same

Assignee: Kabushiki Kaisha Toshiba
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Quick Facts
Patent No.
US 7,075,169
App. No.
10/654,030
Granted
Jul 11, 2006
Kind
B2
Abstract

A hollow region is formed in a silicon substrate. A plurality of openings formed in the silicon layer on the hollow region is filled with a buried film. The bottom portion of the hollow region is formed with a plurality of silicon pillars, which support the silicon layer.

Claims (11)

1. A semiconductor device comprising:

a silicon layer formed on the surface of a silicon substrate;

a source/drain region of a MOS transistor formed in the silicon layer and a body in contact with the source/drain region;

a silicon pillar formed in the silicon substrate under the body;

a hollow region formed in the silicon substrate under the source/drain region; and

a buried layer formed in the silicon layer, the buried layer being located on the hollow region and being in contact with the source/drain region.

2. The device according to claim 1 , further comprising:

a gate insulating film formed on the silicon layer corresponding to the body; and

a gate electrode formed on the gate insulating film.

3. The device according to claim 1 , wherein the buried layer is configured by an insulating film.

4. The device according to claim 1 , wherein the silicon pillar is configured by a single crystal silicon.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 17, 2004
From: MINAMI, YOSHIHIRO; YAMADA, TAKASHI; KOHYAMA, YUSUKE; SATO, TSUTOMU; NAGANO, HAJIME
To: KABUSHIKI KAISHA TOSHIBA
Reel/Frame 014982/0088 →
Priority Claims (1)
JP 2002-259195 · Sep 4, 2002 · national
Continuity (1)
Related Publication 20040124439A1 · Jul 1, 2004