IP Library Granted Patent US 7,015,049
Granted Patent B2
US 7,015,049 · App. 10/654,376 · Granted Mar 21, 2006

Fence-free etching of iridium barrier having a steep taper angle

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 7,015,049
App. No.
10/654,376
Granted
Mar 21, 2006
Kind
B2
Abstract

An Iridium barrier layer is between a contact plug and a bottom electrode of a capacitor. Etching is performed to pattern the bottom electrode and barrier layer using a fluorine-based recipe resulting in the formation of a first fence clinging to the sidewalls. Next the remaining barrier layer is etched using a CO-based recipe. A second fence is formed clinging to and structurally supported by the first fence. At the same time, the CO-based recipe etches away a substantial portion of the first fence to remove the structural support provided to the second fence. The second fence is therefore lifted-off from the sidewalls leaving the sidewalls substantially free of clinging fences. The etched barrier layer has a sidewall transition. The sidewalls have a relatively low taper angle above the sidewall transition and a relatively steep taper angle below the sidewall transition.

Claims (18)

1. A method for manufacturing a ferroelectric capacitor comprising the steps of:

forming a substructure of the capacitor having a contact plug passing therethrough for electrically connecting a bottom electrode of the capacitor to an underlying active layer;

depositing over the substructure the bottom electrode including a barrier layer intermediate therebetween;

depositing over the bottom electrode a ferroeletric layer such that the diffusion of contaminants from the ferroelectric layer to the contact plug is inhibited by the intermediate barrier layer;

depositing over the ferroelectric layer a top electrode;

depositing over the top electrode, the underlying ferroelectric layer and the bottom electrode a first hardmask;

etching to pattern the top electrode using the first hardmask;

depositing over the remaining portions of the first hardmask and on the bottom electrode an additional hardmask;

etching to pattern the bottom electrode using a first recipe resulting in the formation of a first fence clinging to sidewalls of the additional hardmask, bottom electrode and barrier layer; and

etching the intermediate barrier layer using a second recipe resulting in the formation of a second fence clinging to and structurally supported by the first fence while at the same time etching away a substantial portion of the first fence to remove the structural support provided to the second fence so that the second fence is lifted-off from the sidewalls leaving the sidewalls substantially free of clinging fences.

2. The method of claim 1 wherein the intermediate barrier layer has a composition including Iridium.

3. The method of claim 2 , wherein 30% to 90% of the barrier layer not protected by the additional hardmask is removed during the etching using the first recipe.

4. The method of claim 1 , wherein the etching of the intermediate barrier layer using the second recipe continues until portions of the substructure are also etched.

5. The method of claim 1 , wherein the additional hardmask is tapered at an angle steeper than 60 degrees.

6. The method of claim 1 , wherein the contaminants include oxygen.

7. The method of claim 1 , wherein the first recipe is a fluorine-based recipe.

8. The method of claim 1 , wherein the second recipe is a CO-based recipe.

9. The method of claim 1 , wherein the additional hardmask is formed from TEOS.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 15, 2010
From: INFINEON TECHNOLOGIES AG
To: QIMONDA AG
Reel/Frame 023796/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 29, 2003
From: EGGER, ULRICH; ZHUANG, HAOREN; STOJAKOVIC, GEORGE; TOMIOKA, KAZUHIRO
To: INFINEON TECHNOLOGIES AG; KABUSHIKI KAISHA TOSHIBA
Reel/Frame 014837/0226 →