Granted Patent B2

US 7,451,243 · App. 10/655,463 · Granted Nov 11, 2008

Assignee: Alcatel Lucent

Abstract

Claims (43)

1. A method of resetting a slave card electrically connected to an administrative processor of a system via a Reduced Media Independent Interface (“RMII”) Ethernet physical layer device (“PHY”), the method comprising:

responsive to detection of a start of frame indicator (“SFI”), activating a shift register;

shifting reset signal data into the shift register, wherein the reset signal data includes a reset address corresponding to a slave card to be reset;

comparing the reset signal data shifted into the shift register with compare data, wherein the compare data includes strapping data corresponding to the slave card; and

responsive to the reset signal data being the same as the compare data, resetting the slave card.

2. The method of claim 1 further comprising providing to the slave card the strapping data.

3. The method of claim 1 further comprising:

detecting a carrier sense signal; and

responsive to detection of the carrier sense signal, awaiting detection of the SFI.

4. The method of claim 3 further comprising, responsive to the reset signal data being different from the compare data:

disabling the shift register; and

awaiting detection of the carrier sense signal.

5. The method of claim 2 wherein the strapping data identifies a location of the slave card in the system.

6. The method of claim 1 wherein the reset signal data comprises a header portion identifying the data as a reset signal.

7. The method of claim 1 wherein the reset signal data including the reset address identifies a backplane and a slot of the backplane in which a slave card to be reset is installed.

8. The method of claim 1 further comprising defining a non-global, local, 48-bit Ethernet address for use as a reset signal.

9. The method of claim 8 wherein the Ethernet address comprises a standard two-byte header value followed by two bytes of zeros and the reset address corresponding to a slave card to be reset.

10. A circuit for resetting a slave card installed in a system via an Ethernet Reduced Media Independent Interface (“RMII”) physical layer device (“PHY”), the circuit comprising:

an enable circuit connected to receive a carrier sense signal from the RMII PHY;

a shift register connected to the enable circuit, wherein responsive to receipt of the SFI, the enable circuit enables the shift register; and

a comparator connected to the shift register,

wherein when the shift register is enabled, reset signal data including a reset address corresponding to a slave card to be reset is shifted into the shift register, and further wherein when the reset signal data is equal to compare data including strapping data corresponding to the slave card, the comparator outputs a reset signal to reset the slave card.

11. The circuit of claim 1 wherein, when the reset signal data is not equal to the compare data, the shift register is disabled.

12. The circuit of claim 10 wherein the comparator further comprises a memory device for storing the compare data.

13. The circuit of claim 10 wherein the reset signal data is clocked into the shift register via two data lines.

14. The circuit of claim 13 wherein half of the reset signal data is clocked into the shift register via a first one of the data lines and the remainder of the reset signal data is clocked into the shift register via a second one of the data lines.

15. The circuit of claim 10 wherein the reset signal data comprises a non-global, local, 48-bit Ethernet address.

16. The circuit of claim 15 wherein the Ethernet address comprises a standard two-byte header value followed by two bytes of zeros and the reset address corresponding to a slave card to be reset.

17. A circuit for resetting a slave card electrically connected to an administrative processor of a system via a Reduced Media Independent Interface (“RMII”) Ethernet physical layer device (“PHY”), the circuit comprising:

means responsive to detection of a start of frame indicator (“SFI”) for activating a shift register;

means for shifting reset signal data into the shift register, wherein the reset signal data includes a reset address corresponding to a slave card to be reset;

means for comparing the reset signal data shifted into the shift register with compare data, wherein the compare data includes strapping data corresponding to the slave card; and

means responsive to the reset signal data being the same as the compare data for resetting the slave card.

18. The circuit of claim 17 further comprising means for providing to the slave card the strapping data.

19. The circuit of claim 17 further comprising:

means for detecting a carrier sense signal; and

means responsive to detection of the carrier sense signal, awaiting detection of the SFI.

20. The circuit of claim 19 further comprising means responsive to the reset signal data being different from the compare data for disabling the shift register and awaiting detection of the carrier sense signal.

21. The circuit of claim 18 wherein the strapping data identifies a location of the slave card in the system.

22. The circuit of claim 17 wherein the reset signal data comprises a header portion identifying the data as a reset signal.

23. The circuit of claim 17 wherein the reset address corresponding to a slave card to be reset identifies a backplane and a slot of the backplane in which a slave card to be reset is installed.

24. The circuit of claim 17 further comprising means for defining a non-global, 48-bit Ethernet address for use as a reset signal.

25. The circuit of claim 24 wherein the Ethernet address comprises a standard two-byte header value followed by two bytes of zeros and the reset address corresponding to a slave card to be reset.

Assignments (8)

Continuity (2)