Method of manufacturing an ESD protection device with the same mask for both LDD and ESD implantation
View Patent ↗A method of manufacturing a semiconductor device having a first and second transistor of an ESD protection and internal circuit respectively. The method includes the steps of providing a substrate, forming gates of the first and second transistor on the substrate, depositing a mask layer and patterning the mask layer using one single mask to remove the mask layer on the gates, a portion of a drain region of the first transistor, and a source and drain region of the second transistor, implementing ESD implantation under the regions without the patterned mask layer, removing the mask layer and forming sidewall spacers of the gates, and implementing drain diffusion.
1. A semiconductor device comprising:
a substrate;
an internal circuit formed on the substrate, comprising:
a first gate formed on the substrate; and
a first source and drain region formed in the substrate and respectively on both sides of the first gate; and
an electrostatic discharge protection circuit formed on the substrate, comprising:
a second gate formed on the substrate; and
a second source and drain region formed in the substrate and respectively on both sides of the second gate; and
a first and second lightly doped region formed in the substrate, wherein the first lightly doped region surrounds the first drain region, the second lightly doped region is only disposed between the second gate and the second drain region, and the first and second lightly doped region both have a depth greater than that of the first and second drain region.
2. The semiconductor device as claimed in claim 1 , wherein all the source and drain regions are N + doped regions.
3. The semiconductor device as claimed in claim 1 , wherein all the source and drain regions are P + doped regions.
4. The semiconductor device as claimed in claim 1 , wherein the first and second lightly doped regions are N − type ESD implantation regions.
5. The semiconductor device as claimed in claim 1 , wherein the first and second lightly doped regions are P − type ESD implantation regions.