IP Library Granted Patent US 7,323,726
Granted Patent B1
US 7,323,726 · App. 10/658,882 · Granted Jan 29, 2008

Method and apparatus for coupling to a common line in an array

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Quick Facts
Patent No.
US 7,323,726
App. No.
10/658,882
Granted
Jan 29, 2008
Kind
B1
Abstract

A method and apparatus for coupling to a common line in an array. Gate structures of an integrated circuit are formed. Source and drain regions adjacent to the gate structures are implanted. A source contact from a metal Vss line to a source region is formed. Dopants of the source and drain regions diffuse laterally to overlap. The overlapping diffusion regions conduct and couple the drain region to a source region. Beneficially, the drain region is coupled to the metal Vss line. As a beneficial result, source contacts may be formed along a line of drain contacts in associated rows of drain contacts, and coupled to a common source line via the novel overlapping diffusion regions. A plurality of word lines may be formed without any bending in the word lines to accommodate source contacts that are larger than the source line. Numerous deleterious consequences of bent word lines, for example decreased array density and detrimental electrical behavior of memory cells in the vicinity of bent word lines, may beneficially be overcome by embodiments of the present invention.

Claims (14)

1. An integrated circuit device comprising:

an array of flash memory cells, said cells comprising a source, a drain and a stacked gate structure comprising a control gate, a charge trapping layer and an insulating layer, wherein a region under said stacked gate structure comprises overlapping lateral diffusions of implantation regions of said source and said drain;

a common source line coupled with said source; and

a source contact disposed outside of said common source line and coupled with said source, wherein said source contact is coupled to said common source line under said stacked gate structure through said drain, and wherein said source contact is disposed in a row with drain contacts.

2. The integrated circuit device of claim 1 comprising substantially straight word lines.

3. The integrated circuit device of claim 1 wherein said common source line has a substantially uniform width within said array of cells.

4. The integrated circuit device of claim 1 wherein said integrated circuit device comprises a non-volatile memory.

5. The integrated circuit device of claim 4 wherein said charge trapping layer is a floating gate.

6. An integrated circuit device comprising a first non-volatile flash memory cell comprising:

a first stacked gate structure comprising a control gate, a charge trapping layer and an insulating layer;

dopants disposed on either sides of said first stacked gate structure; and

a first region under said first stacked gate structure comprising overlapping lateral diffusions of source and drain implantation regions, wherein said source and drain implantation regions are able to conduct independent of any voltage applied to said first stacked gate structure, wherein said source implantation region is coupled to a common source line, wherein a first source contact is disposed outside of said common source line and coupled with said source implantation region, wherein said first source contact is coupled to said common source line under said first stacked gate structure through said drain implantation region, and wherein said first source contact is disposed in a row of drain contacts.

7. The integrated circuit device of claim 6 further comprising a second non-volatile flash memory cell comprising a second stacked gate structure comprising a control gate, a charge trapping layer and an insulating layer, wherein a second region under said second stacked gate structure comprises overlapping lateral diffusions of source and drain implantation regions.

8. The integrated circuit device of claim 7 wherein the source region associated with said second stacked gate structure is coupled to a second source contact, wherein said second source contact is coupled with said common source line and disposed outside of said common source line, wherein said second source contact is coupled to said common source line under said second stacked gate structure, and wherein said second source contact is disposed in a row of drain contacts.

Assignments (8)
CORRECTIVE ASSIGNMENT TO CORRECT THE 8647899 PREVIOUSLY RECORDED ON REEL 035240 FRAME 0429. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTERST. Recorded Nov 3, 2020
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 058002/0470 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 30, 2015
From: SPANSION, LLC
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 036037/0001 →
SECURITY INTEREST Recorded Mar 21, 2015
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 035240/0429 →
RELEASE OF SECURITY INTEREST Recorded Mar 13, 2015
From: BARCLAYS BANK PLC
To: SPANSION LLC; SPANSION INC.; SPANSION TECHNOLOGY LLC
Reel/Frame 035201/0159 →
SECURITY AGREEMENT Recorded Jun 4, 2010
From: SPANSION LLC; SPANSION INC.; SPANSION TECHNOLOGY INC.; SPANSION TECHNOLOGY LLC
To: BARCLAYS BANK PLC
Reel/Frame 024522/0338 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 26, 2007
From: SPANSION INC.
To: SPANSION LLC
Reel/Frame 019065/0945 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 19, 2007
From: ADVANCED MICRO DEVICES, INC.
To: SPANSION INC.
Reel/Frame 019030/0331 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 9, 2003
From: CHANG, KUO-TUNG; SUN, YU
To: ADVANCED MICRO DEVICES, INC.
Reel/Frame 014480/0921 →