Adaptive equalization using a conditional update sign-sign least mean square algorithm
View Patent ↗An adaptive equalizer finite impulse response (FIR) filter for high-speed communication channels with modest complexity, where the filter is iteratively updated during a training sequence by a circuit performing the update: h ( t+ 1 ) = h ( t ) +μ[sgn{d ( t ) }−sgn{z ( t ) −Kd ( t ) }]sgn{ x ( t )}, where h (t) is the filter vector representing the filter taps of the FIR filter, x (t) is the data vector representing present and past samples of the received data x(t), d(t) is the desired data used for training, z(t) is the output of the FIR filter, μ determines the memory or window size of the adaptation, and K is a scale factor taking into account practical limitations of the communication channel, receiver, and equalizer. Furthermore, a procedure and circuit structure is provided for calibrating the scale factor K.
1. An apparatus comprising:
a circuit including a discrete-time FIR (Finite Impulse Response) filter comprising n multiplier units to implement a filter response [ h (t)] i , i=0, 1, . . . , n−1, where t is a time index, the FIR filter to filter a discrete-time sequence of input voltages x(t) to provide a sequence of filtered output voltages z(t) where
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and
a data generator coupled to the discrete-time FIR filter, the data generator to provide a discrete-time sequence of desired voltages d(t), t=1, 2, . . . , T;
wherein for t=1, 2, . . . , T, the filter response satisfies an update relationship [ h (t+1)] i =[ h (t)] i +μ[sgn{d(t)}−sgn{z(t)−Kd(t)}]sgn{x(t−i)}, i=0, 1, . . . , n−1, where μ and K are scalars and sgn{ } denotes sign.
2. The apparatus as set forth in claim 1 , wherein each multiplier unit comprises a voltage-to-current converter and a current steering digital-to-analog converter.
3. The apparatus as set forth in claim 1 , wherein the voltages x(t), z(t), and d(t) are differential voltages.
4. An apparatus comprising:
a circuit including a discrete-time FIR (Finite Impulse Response) filter to filter a discrete-time input sequence of voltages x(t) where t is a discrete-time index, to provide, for t=1, 2, . . . , T, a voltage indicative of
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where
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i=0, 1, . . . , n−1 are n weights indexed by t;
a data generator coupled to the filter to provide a discrete-time sequence of desired voltages d(t), t=1, 2, . . . , T;
a latch circuit coupled to the filter to provide, for t=1, 2, . . . , T, a voltage indicative of sgn{z(t)−Kd(t)} where K is a weight and sgn{ } denotes the sign function;
a digital summer coupled to the filter to provide, for t=1, 2, . . . , T, n voltages indicative of sgn{d(t)}−sgn{z(t)−Kd(t)}, i=0, 1, . . . , n−1;
a digital multiplier coupled to the filter to provide, for t=1, 2, . . . , T, n voltages indicative of μ[sgn{d(t)}−sgn{z(t)−Kd(t)}]sgn{x(t−i)}, i=0, 1, . . . , n−1 where μ is a weight;
a digital summer and a delay element coupled to the filter to provide to the FIR filter, for t=1, 2, . . . , T, n voltages indicative of [ h (t)] i +μ[sgn{d(t)}−sgn{z(t)−Kd(t)}]sgn{x(t−i)}, i=0, 1, . . . , n−1 so that for t=1, 2, . . . , T the weights [ h (t+1)] i , i=0, 1, . . . , n−1 are given by [ h (t+1)] i +[ h (t)] i +μ[sgn{d(t)}−sgn{z(t)−Kd(t)}]sgn{x(t−i)}, i=0, 1, . . . , n−1.
5. The apparatus as set forth in claim 4 , the FIR filter comprising n multiplier units, each multiplier unit, denoted as multiplier unit(i), i=0, 1, . . . , n−1, each multiplier unit(i), i=0, 1, . . . , n−1, comprising:
a voltage-to-current converter(i) to provide as output a current I VC (i) indicative of the voltage x(t−i); and
a current steering digital-to-analog converter(i) to shunt a portion of I VC (i) to provide as output at time t a current indicative of [ h (t)] i , x(t−i).
6. The apparatus as set forth in claim 5 , further comprising:
a multiplier unit comprising:
a voltage-to-current converter to provide as output a current I VC indicative of the voltage d(t); and
a current steering digital-to-analog converter to shunt a portion of I VC to provide as output at time t a current indicative of Kd(t).
7. The apparatus as set forth in claim 4 , wherein the voltages x(t), z(t), and d(t) are differential voltages.
8. A computer system comprising:
a board comprising a first transmission line and a second transmission line; and
a receiver coupled to the first and second transmission lines, the receiver comprising:
a discrete-time FIR (Finite Impulse Response) filter comprising n multiplier units to implement a filter response [ h (t)] i , i=0, 1, . . . , n−1, where t is a time index, the FIR filter to filter a discrete-time sequence of input voltages x(t) to provide a sequence of filtered output voltages z(t) where
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-
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[
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;
and
a data generator to provide a discrete-time sequence of desired voltages d(t), t=1, 2, . . . , T;
wherein for t=1, 2, . . . , T, the filter response satisfies an update relationship [ h (t+1)] i =[ h (t)] i +μ[sgn{d(t)}−sgn{z(t)−Kd(t)}]sgn{x(t−i)}, i=0, 1, . . . , n−1, where μ and K are scalars and sgn{ } denotes sign.
9. The computer system as set forth in claim 8 , wherein each multiplier unit comprises a voltage-to-current converter and a current steering digital-to-analog converter.
10. The computer system as set forth in claim 8 , wherein the voltages x(t), z(t), and d(t) are differential voltages.