Multiple parallel pipeline processor having self-repairing capability
View Patent ↗A multiple parallel pipeline digital processing apparatus has the capability to substitute a second pipeline for a first in the event that a failure is detected in the first pipeline. Preferably, a redundant pipeline is shared by multiple primary pipelines. Preferably, the pipelines are located physically adjacent one another in an array. A pipeline failure causes data to be shifted one position within the array of pipelines, to by-pass the failing pipeline, so that each pipeline has only two sources of data, a primary and an alternate. Preferably, selection logic controlling the selection between a primary and alternate source of pipeline data is integrated with other pipeline operand selection logic.
1. A digital data processing apparatus, comprising:
at least one processor, each said at least one processor executing at least one respective thread of processor-executable instructions, said at least one processor collectively including:
(a) a plurality of parallel pipelines, each pipeline of said plurality of parallel pipelines having the capability to perform a set of pre-defined functions on respective input data; and
(b) control logic controlling the routing of data to said plurality of parallel pipelines, wherein said control logic, responsive to detection of a failure of a first pipeline of said plurality of parallel pipelines, causes data intended for processing by said first pipeline to be processed by a second pipeline of said plurality of parallel pipelines.
2. The digital data processing apparatus of claim 1 , wherein said plurality of parallel pipelines comprises at least one redundant pipeline.
3. The digital data processing apparatus of claim 2 , wherein said plurality of parallel pipelines comprises N primary pipelines and a single redundant pipeline, said redundant pipeline providing redundant function in the event of failure of any single one of said N primary pipelines, where N is greater than 1.
4. The digital data processing apparatus of claim 1 , wherein said control logic comprises selection logic at one or more inputs to each respective pipeline, said selection logic controlling the selection between a primary source and a secondary source of pipeline data for the respective pipeline.
5. The digital data processing apparatus of claim 4 , wherein said selection logic is integrated with operand source selection logic for one or more stages of the respective pipeline.
6. The digital data processing apparatus of claim 1 , wherein said at least one processor is a plurality of processors, said plurality of processors sharing at least one of said plurality of parallel pipelines.
7. The digital data processing apparatus of claim 6 , wherein said plurality of processors shares a redundant pipeline of said plurality of parallel pipelines.
8. The digital data processing apparatus of claim 1 , wherein said plurality of parallel pipelines perform arithmetic operations on floating point data.
9. The digital data processing apparatus of claim 8 , wherein said plurality of parallel pipelines perform arithmetic operations on mixed data, including floating point data and fixed point data.
10. The digital data processing apparatus of claim 1 , further comprising:
a plurality of processors;
a memory storing instructions for execution on said plurality of processors; and
at least one bus coupling said plurality of processors to said memory.
11. A processor, comprising:
a plurality of parallel pipelines, each pipeline of said plurality of parallel pipelines having the capability to perform a set of pre-defined functions on respective input data, said plurality of parallel pipelines including at least one redundant pipeline; and
control logic controlling the routing of data to said plurality of parallel pipelines, wherein said control logic, responsive to detection of a failure of a first pipeline of said plurality of parallel pipelines, causes data intended for processing by said first pipeline to be processed by a second pipeline of said plurality of parallel pipelines.
12. The processor of claim 11 , wherein said plurality of parallel pipelines comprises N primary pipelines and a single redundant pipeline, said redundant pipeline providing redundant function in the event of failure of any single one of said N primary pipelines, where N is greater than 1.
13. The processor of claim 11 , wherein said control logic comprises selection logic at one or more inputs to each respective pipeline, said selection logic controlling the selection between a primary source and a secondary source of pipeline data for the respective pipeline.
14. The processor of claim 13 , wherein said selection logic is integrated with operand source selection logic for one or more stages of the respective pipeline.
15. The processor of claim 11 , wherein said plurality of parallel pipelines perform arithmetic operations on floating point data.
16. The processor of claim 15 , wherein said plurality of parallel pipelines perform arithmetic operations on mixed data, including floating point data and fixed point data.