Semiconductor device using current mirror circuit
View Patent ↗The semiconductor device includes a first current mirror circuit combining analog power sources and digital power sources to receive small amplitude signals and constant-voltage input signals, a second current mirror circuit for receiving a signal output from the first current mirror circuit and for level-converting the signal from analog power source to digital power source, a first node provided in the first current mirror circuit, a second node provided in the second current mirror circuit, and an inverter circuit for receiving a signal output on the basis of the voltage levels of the first node and the second node and for outputting a CMOS level signal.
1. A semiconductor device, comprising:
a first current mirror circuit combining an analog power source and a digital power source to receive a small amplitude signal and a constant-voltage input signal;
a second current mirror circuit for receiving a signal output from the first current mirror circuit and for level-converting the signal from analog power source to digital power source;
a first node provided in the first current mirror circuit;
a second node provided in the second current mirror circuit; and
an inverter circuit for receiving a signal output on the basis of voltage levels of the first node and the second node and for outputting a CMOS level signal,
wherein a CMOS level signal is generated from the small amplitude signal.
2. The semiconductor device according to claim 1 , wherein:
the first current mirror circuit comprises a plurality of first PMOS transistors and a plurality of first NMOS transistors,
the second current mirror circuit comprises a pair of second PMOS transistors and a pair of second NMOS transistors,
the inverter circuit comprises a pair of third PMOS transistors and a pair of third NMOS transistors.
3. The semiconductor device according to claim 2 , wherein:
the number of the first PMOS transistors is six, and the number of the first NMOS transistors is four.
4. The semiconductor device according to claim 1 , wherein:
the digital power source of the first current mirror circuit and the digital power source of the inverter circuit are set at the same potential.
5. The semiconductor device according to claim 1 , wherein:
a potential of an input signal to the inverter circuit coincides with a logic threshold of an input of the inverter circuit.
6. The semiconductor device according to claim 5 , wherein:
the potential of the input signal and the logic threshold are set to coincide with each other so as to set a duty within a range of a predetermined target value.
7. The semiconductor device according to claim 1 , wherein:
the semiconductor device is a direct Rambus DRAM.