Dual trench isolation using single critical lithographic patterning
View Patent ↗A method and apparatus for forming shallow and deep isolation trenches in a substrate so that the shallow and deep isolation trenches are aligned without mis-registration. The method includes forming a plurality of shallow trenches, covering a portion of the plurality of shallow trenches, then etching the uncovered shallow trenches to create deeper trenches.
1. An isolation structure, comprising:
a first area and a second area;
a plurality of shallow isolation trenches in the first area; and
a plurality of deep isolation trenches in the second area, wherein the deep isolation trenches and the shallow isolation trenches are self-aligned using a single photolithography step and at least one shallow isolation trench has a width equal to or greater than the width of at least one deep isolation trench.
2. The isolation structure of claim 1 , wherein the plurality of shallow trenches are between approximately 1000 Å to 2000 Å in depth.
3. The isolation structure of claim 1 , wherein the plurality of deep isolation trenches are between approximately 3000 Å to 6000 Å in depth.
4. The isolation structure of claim 1 , wherein the first area includes memory devices.
5. The isolation structure of claim 4 , wherein the memory devices comprise flash memory devices.
6. The isolation structure of claim 1 , wherein the second area includes logic devices.
7. The isolation structure of claim 1 , wherein the second area includes only deep isolation trenches.
8. The isolation structure of claim 1 , further comprising:
a thin thermal oxide in the shallow isolation trenches.
9. The isolation structure of claim 1 , further comprising:
a trench fill material in the shallow isolation trenches.
10. The isolation structure of claim 1 , further comprising:
a first active region in the first area; and
a second active region in the second area.
11. The isolation structure of claim 10 , further comprising:
a mask layer on the first active region.
12. The isolation structure of claim 11 , wherein the mask layer comprises a pad oxide layer and a nitride layer.
13. The isolation structure of claim 12 , wherein the mask layer comprises an antireflective coating.
14. The isolation structure of claim 1 , further comprising:
a photoresist layer covering the first area, wherein the photoresist layer leaves the second area exposed.
15. An apparatus comprising:
a substrate having shallow isolation trenches in a first area and deep isolation trenches in a second area, wherein the deep and shallow isolation trenches are self-aligned using a single photolithography step; and
a photoresist layer covering the first area and leaving the second area exposed.
16. The apparatus of claim 15 , wherein the substrate comprises monocrystalline silicon.
17. The apparatus of claim 15 , wherein the shortest distance between a shallow isolation trench and an adjacent deep isolation trench is greater than the allowed error of a non-critical photolithography mask.
18. The apparatus of claim 17 , wherein the allowed error is in the range of about 150 to 300 nm.
19. The apparatus of claim 15 , further comprising:
a first active region in the first area; and
a second active region in the second area.
20. The apparatus of claim 15 , further comprising:
a mask layer on the first active region, wherein the mask layer comprises a pad oxide layer and a nitride layer.
21. The apparatus of claim 15 , wherein the mask layer comprises an antireflective coating.
22. An apparatus comprising:
a substrate including a first area and a second area;
a plurality of shallow isolation trenches in the first area;
a plurality of deep isolation trenches in the second area, wherein the deep isolation trenches and the shallow isolation trenches are self-aligned using a single photolithography step and at least one shallow isolation trench has a width equal to or greater than the width of at least one deep isolation trench;
a plurality of memory devices in the first area; and
a plurality of logic devices in the second area.
23. The apparatus of claim 22 , wherein the memory devices comprise flash memory devices.
24. The apparatus of claim 23 , wherein the logic devices comprise transistors to control the flash memory devices.