Patent Assignment
Reel/Frame 067305/0491
Assignment of Assignor's Interest
Recorded: 2024-05-02
Pages: 18
Assignor
INTEL CORPORATION
Executed: 2024-03-28
Assignee
INTEL NDTM US LLC
2200 MISSION COLLEGE BOULEVARD, SANTA CLARA, CALIFORNIA, 95054
Covered Properties
(60)
Dual Trench Isolation Using Single Critical Lithographic Patterning
Vertical Memory Device and Method
Reclaim Algorithm for Fast Edits in a Nonvolatile File System
Techniques to store configuration information in an option read-only memory
Flash Memory and Associated Methods for Reading and Writing
Application:
11/618,652 →
Publication:
US 2008/0158986
Nibble Encoding for Improved Reliability of Non-Volatile Memory
Flash Memory Having a Floating Gate in the Shape of a Curved Section
Application:
12/629,992 →
Publication:
US 2011/0133266
Ddr Flash Implementation with Direct Register Access to Legacy Flash Functions
Application:
13/189,683 →
Publication:
US 2012/0191898
Pitch Division Patterning Techniques
Application:
13/431,772 →
Publication:
US 2012/0181705
Extended Select Gate Lifetime
Using Counters and a Table to Protect Data in a Storage Device
Application:
15/479,224 →
Publication:
US 2017/0269837
Memory Cell Sensing Circuit with Adjusted Bias from Pre-Boost Operation
Read Latency Reduction for Partially-Programmed Block of Non-Volatile Memory
Vertical Channel with Conductive Structures to Improve String Current
Application:
17/123,451 →
Publication:
US 2022/0189987
Persistent Data Structure to Track and Manage Ssd Defects
Dynamic Detection and Dynamic Adjustment of Sub-Threshold Swing in a Memory Cell Sensing Circuit
Nand Sensing Circuit and Technique for Read-Disturb Mitigation
Modulation of Source Voltage in Nand-Flash Array Read
Simultaneous Programming of Multiple Sub-Blocks in Nand Memory Structures
Staggered Active Bitline Sensing
Techniques to Calibrate an Impedance Level
Three-Dimensional (3D) Nand Component with Control Circuitry Across Multiple Wafers
Application:
17/314,979 →
Publication:
US 2022/0359441
Program Verify Process Having Placement Aware Pre-Program Verify (Ppv) Bucket Size Modulation
Staggered Read Recovery for Improved Read Window Budget in a Three Dimensional (3D) Nand Memory Array
Split Block Array for 3D Nand Memory
3D Nand with Inter-Wordline Airgap
Independent Multi-Page Read Operation Enhancement Technology
Metal Hybrid Charge Storage Structure for Memory
Page Map Renumbering to Reduce Error Correction Failures and Improve Program Time Uniformity
Application:
17/393,877 →
Publication:
US 2023/0044991
Lean Command Sequence for Multi-Plane Read Operations
Dynamic Gate Steps for Last-Level Programming to Improve Write Performance
Non-Conductive Etch Stop Structures for Memory Applications with Large Contact Height Differential
3D Memory Device with Top Wordline Contact Located in Protected Region During Planarization
3D Nand with Io Contacts in Isolation Trench
Grouped Global Wordline Driver with Shared Bias Scheme
Block List Management for Wordline Start Voltage
Chuck with Non-Flat Shaped Surface
Pump Discharge Sequence Improvements in External Power Supply Mode for Pulse Recovery Phases in Non-Volatile Memory
Additional Silicide Layer on Top of Staircase for 3D Nand Wl Contact Connection
Selective Etch Stop for Wordline Contacts in Vertical 3D Nand Staircase Regions
3D Nand Memory Cell with Flat Trap Base Profile
Application:
17/551,018 →
Publication:
US 2023/0164987
Tier Expansion Offset
Parallel Staircase 3D Nand
Dummy Wordline Contacts to Improve Etch Margin of Semi-Isolated Wordlines in Staircase Structures
Varying Channel Width in Three-Dimensional Memory Array
Application:
17/791,175 →
Publication:
US 2023/0033086
Block-To-Block Isolation and Deep Contact Using Pillars in a Memory Array
Method and Apparatus to Mitigate Hot Electron Read Disturbs in 3D Nand Devices
Organic Spacer for Integrated Circuits
Application:
17/919,730 →
Publication:
US 2023/0163045
Method and Apparatus to Mitigate Word Line Staircase Etch Stop Layer Thickness Variations in 3D Nand Devices
Structure and Method of Increasing Subtractive Bitline Air Gap Height
Application:
18/047,094 →
Publication:
US 2023/0065187
Word Line Voltage Detection Circuit for Enchanced Read Operation
Application:
18/047,097 →
Publication:
US 2023/0079077
Nand Aging Protection Scheme
Application:
18/147,335 →
Publication:
US 2024/0220129
Multi-Phase Clocking Scheme for a Memory Device
Application:
18/148,230 →
Publication:
US 2023/0215478
Techniques for Preventing Read Disturb in Nand Memory
Integrated Word Line Contact Structures in Three-Dimensional (3D) Memory Array
Application:
18/235,766 →
Publication:
US 2023/0402389
Memory Devices with Gradient-Doped Control Gate Material
Application:
18/249,635 →
Publication:
US 2023/0395729
Large Grain and Halogen-Free Silicon Cell Channel for 3D Nand String
Application:
18/367,319 →
Publication:
US 2023/0422506
Floating Gate Structures
Application:
61/052,958 →
Automatic Self-Disabling Input Buffer
Application:
61/504,493 →
Disaggregated Rack Mount Storage Side Transaction Support
Application:
62/916,176 →
Related Assignments
(15)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest
Feb 16, 2010
From: MICRON TECHNOLOGY, INC.
To: INTEL CORPORATION
Reel/Frame 023945/0842 →
Assignment of Assignor's Interest
Mar 23, 2014
From: KUTERGIN, TIMOFEY
To: INTEL CORPORATION
Reel/Frame 032503/0695 →
Assignment of Assignor's Interest
Mar 23, 2014
From: SAMYLIN, SERGEY
To: INTEL CORPORATION
Reel/Frame 032503/0708 →
Assignment of Assignor's Interest
Feb 25, 2016
From: WAKCHAURE, YOGESH B.; PANGAL, KIRAN; GUO, XIN; MENG, QINGRU
To: INTEL CORPORATION
Reel/Frame 037834/0141 →
Assignment of Assignor's Interest
Oct 28, 2016
From: MICRON TECHNOLOGY, INC.
To: INTEL CORPORATION
Reel/Frame 040163/0162 →
Assignment of Assignor's Interest
Dec 1, 2020
From: RAJWADE, SHANTANU R.; NASRI, BAYAN; FANG, TZU-NING; HAQUE, REZAUL
To: INTEL CORPORATION
Reel/Frame 054557/0523 →
Assignment of Assignor's Interest
Dec 4, 2020
From: DOLLER, JOSEPH F.; GAEWSKY, KRISTOPHER H.; MEBANE, NOAH
To: INTEL CORPORATION
Reel/Frame 054551/0021 →
Assignment of Assignor's Interest
Jan 27, 2021
From: PRABHU, NAVEEN VITTAL; MADRASWALA, ALIASGAR; SHENOY, ROHIT; NATARAJAN, SHANKAR
To: INTEL CORPORATION
Reel/Frame 055051/0173 →
Assignment of Assignor's Interest
Feb 8, 2021
From: MEBRAHTU, HENOK T.; AGARWAL, RAHUL; KOVAL, RANDY J.; HUANG, GUANGYU
To: INTEL CORPORATION
Reel/Frame 055180/0510 →
Assignment of Assignor's Interest
Feb 9, 2021
From: AMEEN BESHARI, TAREK AHMED; RAJWADE, SHANTANU R.; AMANI, MATIN; RAMANAN, NARAYANAN
To: INTEL CORPORATION
Reel/Frame 055195/0792 →
Assignment of Assignor's Interest
Mar 30, 2021
From: RAMANAN, NARAYANAN
To: INTEL CORPORATION
Reel/Frame 055766/0052 →
Assignment of Assignor's Interest
Mar 30, 2021
From: RAMANAN, NARAYANAN
To: INTEL CORPORATION
Reel/Frame 055765/0854 →
Assignment of Assignor's Interest
Mar 21, 2022
From: KHAKIFIROOZ, ALI; KALAVADE, PRANAV; RAJWADE, SHANTANU; AMEEN BESHARI, TAREK AHMED
To: INTEL CORPORATION
Reel/Frame 059321/0778 →
Assignment of Assignor's Interest
Sep 17, 2025
From: INTEL CORPORATION
To: SK HYNIX NAND PRODUCT SOLUTIONS CORP. (DBA SOLIDIGM)
Reel/Frame 072914/0491 →
Assignment of Assignor's Interest
Sep 18, 2025
From: INTEL CORPORATION
To: INTEL NDTM US LLC
Reel/Frame 072293/0744 →