Program verify process having placement aware pre-program verify (PPV) bucket size modulation

1. An apparatus, comprising:

controller logic circuitry to perform a program-verify programming process to a flash memory chip, wherein, the program-verify programming process is to reduce a size of a pre-program verify (PPV) bucket in response to a number of cells being fully programmed to a same digital state, the number of cells being less than a total number of cells to be programmed to the same digital state,

wherein cells in the PPV bucket comprise cells having read voltage that is less than a first read verify voltage threshold (“VFY”) corresponding to the same digital state and above a second verification read voltage threshold (pre-verify (P-VFY)) that is less than VFY.

2. The apparatus of claim 1 wherein the number of cells are fully programmed after a sequence of program-verify iterations have been performed.

3. The apparatus of claim 1 wherein the number of cells are fully programmed after another total number of cells to be programmed to a lower digital state are fully programmed.

4. The apparatus of claim 3 wherein the lower digital state is the lowest digital state.

5. The apparatus of claim 1 wherein the controller logic circuitry is configured to reduce the size of the PPV bucket more than once per sequence of program-verify operations for the same digital state.

6. The apparatus of claim 1 wherein the reduction of the size of the PPV bucket results in elimination of the PPV bucket.

7. A computing system, comprising:

a plurality of processing cores;

a main memory;

a peripheral control hub; and,

a solid state drive coupled to the peripheral control hub, the solid state drive comprising a controller, the controller comprising logic circuitry to perform a program-verify programming process to a flash memory chip, wherein, the program-verify programming process is to reduce a size of a pre-program verify (PPV) bucket in response to a number of cells being fully programmed to a same digital state, the number of cells being less than a total number of cells to be programmed to the same digital state,

wherein cells in the PPV bucket comprise cells having read voltage that is less than a first read verify voltage threshold (VFY) corresponding to the same digital state and above a second verification read voltage threshold (pre-verify (P-VFY)) that is less than VFY.

8. The computing system of claim 7 wherein the number of cells are fully programmed after a sequence of program-verify iterations have been performed.

9. The computing system of claim 7 wherein the number of cells are fully programmed after another total number of cells to be programmed to a lower digital state are fully programmed.

10. The computing system of claim 9 wherein the lower digital state is the lowest digital state.

11. The computing system of claim 7 wherein the controller is to reduce the size of the PPV bucket more than once per sequence of program-verify operations for the same digital state.

12. The computing system of claim 7 wherein the reduction of the size of the PPV bucket results in elimination of the PPV bucket.

13. A non-transitory machine readable storage medium having stored thereon program code instructions that when processed by a controller causes a controller to perform a program-verify process comprising:

applying a program voltage to a plurality of flash cells that are being programmed to a same digital state;

reading from each of the flash cells to verify which ones of the flash cells are storing a sufficient amount of charge for the digital state; and,

reducing a size of a PPV bucket for future program verify operations for the same digital state because a total number of flash cells that are storing the sufficient amount of charge and are to be programmed to the same digital state has reached a threshold,

wherein cells in the PPV bucket comprise cells having read voltage that is less than a first read verify voltage threshold (VFY) corresponding to the same digital state and above a second verification read voltage threshold (pre-verify (P-VFY)) that is less than VFY.

14. The non-transitory machine readable storage medium of claim 13 wherein the threshold is reached upon a number of program-verify iterations having been performed.

15. The non-transitory machine readable storage medium of claim 13 wherein a condition for the threshold being reached is a lower digital state being fully programmed.

16. The non-transitory machine readable storage medium of claim 13 wherein the program-verify process further comprises reducing the size of the PPV bucket more than once per sequence of program-verify operations for the same digital state.

17. The non-transitory machine readable storage medium of claim 13 wherein the reduction of the size of the PPV bucket results in elimination of the PPV bucket.

18. The apparatus of claim 1 , wherein the controller logic circuitry is to:

apply a first program voltage (V PRG_1 ) to a word line coupled to a plurality of cells;

for cells among the plurality of cells with a nominal bit line voltage V BL , determine whether the cell has a read voltage that meets VFY, falls in the PPV bucket, or has a read voltage that is less than P-VFY;

for cells not meeting VFY,

apply an elevated second program voltage V PRG_2 =V PRG_1 +ΔV PRG to the word line;

for cells with a read voltage less than P-VFY, apply nominal bit line voltage V BL ; and

for cells in the PPV bucket, apply a bit line voltage V BL +ΔV that is above nominal bit line voltage V BL .

19. The computing system of claim 8 , wherein the logic circuitry is to:

apply a first program voltage (V PRG_1 ) to a word line coupled to a plurality of cells;

for cells among the plurality of cells with a nominal bit line voltage V BL , determine whether the cell has a read voltage that meets VFY, falls in the PPV bucket, or has a read voltage that is less than P-VFY;

for cells not meeting VFY,

apply an elevated second program voltage V PRG_2 =V PRG_1 +ΔV PRG to the word line;

for cells with a read voltage less than P-VFY, apply nominal bit line voltage V BL ; and

for cells in the PPV bucket, apply a bit line voltage V BL +ΔV that is above nominal bit line voltage V BL .

20. The non-transitory machine readable storage medium of claim 13 , wherein the program code instructions when processed by the controller further cause the controller to:

apply a first program voltage (V PRG_1 ) to a word line coupled to a plurality of cells;

for cells among the plurality of cells with a nominal bit line voltage V BL , determine whether the cell has a read voltage that meets VFY, falls in the PPV bucket, or has a read voltage that is less than P-VFY;

for cells not meeting VFY,

apply an elevated second program voltage V PRG_2 =V PRG_1 +ΔV PRG to the word line;

for cells with a read voltage less than P-VFY, apply nominal bit line voltage V BL ; and

for cells in the PPV bucket, apply a bit line voltage V BL +ΔV that is above nominal bit line voltage V BL .