Independent multi-page read operation enhancement technology
Systems, apparatuses and methods may provide for technology that sends a first command to a NAND die, sends first address information to the NAND die, and sends a second command to the NAND die, wherein the first command and the second command define a first command sequence and wherein the first address information signal a beginning of a first asynchronous read request from a first plurality of planes. In one example, the technology also sends a second command sequence and second address information to the NAND die wherein the second command sequence signals an end of the first asynchronous read request.
1. A memory device comprising:
a NAND die; and
a controller including logic coupled to one or more substrates, the logic to:
send a first command to the NAND die,
send first address information to the NAND die,
send a second command to the NAND die, wherein the first command and the second command define a first command sequence, and wherein the first command sequence and the first address information signal a beginning of a first asynchronous read request from a first plurality of planes, and
send the first command sequence and third address information to the NAND die, wherein the first command sequence and the third address information signal a beginning of a second asynchronous read request from a second plurality of planes, and wherein the first and second asynchronous read requests are performed concurrently on multiple plane groups, wherein each plane group comprises multiple planes.
2. The memory device of claim 1 , wherein the logic is further to send a second command sequence and second address information to the NAND die, wherein the second command sequence signals an end of the first asynchronous read request.
3. The memory device of claim 2 , wherein the first address information is to identify a first plane in the first plurality of planes and the second address information is to identify a second plane in the first plurality of planes.
4. The memory device of claim 2 , wherein the logic is further to:
send the second command sequence and fourth address information to the NAND die, wherein the second command sequence signals an end of the second asynchronous read request.
5. The memory device of claim 4 , wherein memory cells in the first plurality of planes are to be coded with a different number of bits than memory cells in the second plurality of planes.
6. The memory device of claim 2 , wherein the second command sequence is to include the first command and a third command.
7. A semiconductor apparatus comprising:
one or more substrates; and
logic coupled to the one or more substrates, wherein the logic is implemented at least partly in one or more of configurable or fixed-functionality hardware logic, the logic coupled to the one or more substrates to:
send a first command to a NAND die;
send first address information to the NAND die;
send a second command to the NAND die, wherein the first command and the second command define a first command sequence, and wherein the first command sequence and the first address information signal a beginning of a first asynchronous read request from a first plurality of planes; and
send the first command sequence and third address information to the NAND die, wherein the first command sequence and the third address information signal a beginning of a second asynchronous read request from a second plurality of planes, and wherein the first and second asynchronous read requests are performed concurrently on multiple plane groups, wherein each plane group comprises multiple planes.
8. The semiconductor apparatus of claim 7 , wherein the logic coupled to the one or more substrates is further to send a second command sequence and second address information to the NAND die, wherein the second command sequence signals an end of the first asynchronous read request.
9. The semiconductor apparatus of claim 8 , wherein the first address information is to identify a first plane in the first plurality of planes and the second address information is to identify a second plane in the first plurality of planes.
10. The semiconductor apparatus of claim 8 , wherein the logic coupled to the one or more substrates is further to:
send the second command sequence and fourth address information to the NAND die, wherein the second command sequence signals an end of the second asynchronous read request.
11. The semiconductor apparatus of claim 10 , wherein memory cells in the first plurality of planes are to be coded with a different number of bits than memory cells in the second plurality of planes.
12. The semiconductor apparatus of claim 8 , wherein the second command sequence is to include the first command and a third command.
13. At least one computer readable storage medium comprising a set of instructions, which when executed by a computing system, cause the computing system to:
send a first command to a NAND die;
send first address information to the NAND die;
send a second command to the NAND die, wherein the first command and the second command define a first command sequence, and wherein the first command sequence and the first address information signal a beginning of a first asynchronous read request from a first plurality of planes; and
send the first command sequence and third address information to the NAND die, wherein the first command sequence and the third address information signal a beginning of a second asynchronous read request from a second plurality of planes, and wherein the first and second asynchronous read requests are performed concurrently on multiple plane groups, wherein each plane group comprises multiple planes.
14. The at least one computer readable storage medium of claim 13 , wherein the instructions, when executed, further cause the computing system to send a second command sequence and second address information to the NAND die, wherein the second command sequence signals an end of the first asynchronous read request.
15. The at least one computer readable storage medium of claim 14 , wherein the first address information is to identify a first plane in the first plurality of planes and the second address information is to identify a second plane in the first plurality of planes.
16. The at least one computer readable storage medium of claim 14 , wherein the instructions, when executed, further cause the computing system to:
send the second command sequence and fourth address information to the NAND die, wherein the second command sequence signals an end of the second asynchronous read request.
17. The at least one computer readable storage medium of claim 16 , wherein memory cells in the first plurality of planes are to be coded with a different number of bits than memory cells in the second plurality of planes.
18. The at least one computer readable storage medium of claim 14 , wherein the second command sequence is to include the first command and a third command.
19. A method comprising:
sending a first command to a NAND die;
sending first address information to the NAND die;
sending a second command to the NAND die, wherein the first command and the second command define a first command sequence, and wherein the first command sequence and the first address information signal a beginning of a first asynchronous read request from a first plurality of planes; and
sending the first command sequence and third address information to the NAND die, wherein the first command sequence and the third address information signal a beginning of a second asynchronous read request from a second plurality of planes, and wherein the first and second asynchronous read requests are performed concurrently on multiple plane groups, wherein each plane group comprises multiple planes.
20. The method of claim 19 , further including sending a second command sequence and second address information to the NAND die, wherein the second command sequence signals an end of the first asynchronous read request.