LARGE GRAIN AND HALOGEN-FREE SILICON CELL CHANNEL FOR 3D NAND STRING
An example of an apparatus may include an array of linear cell channels and a string of NAND memory cells arranged along a cell channel of the array of linear cell channels, where a polysilicon cell channel layer comprises material with less than E17 halogen atoms per cubic centimeter, where a thickness of the polysilicon cell channel layer is less than or equal to 25 nanometers, and where an area-weighted grain height mean of the polysilicon cell channel layer is greater than 30 nanometers. Other examples are disclosed and claimed.
1 . An apparatus, comprising:
an array of linear cell channels; and
a string of NAND memory cells arranged along a cell channel of the array of linear cell channels, wherein a polysilicon cell channel layer comprises material with less than E17 halogen atoms per cubic centimeter, wherein a thickness of the polysilicon cell channel layer is less than or equal to 25 nanometers, and wherein an area-weighted grain height mean (AWGHM) of the polysilicon cell channel layer is greater than 30 nanometers.
2 . The apparatus of claim 1 , wherein the polysilicon cell channel layer comprises less than E16 halogen atoms per cubic centimeter.
3 . The apparatus of claim 1 , wherein the polysilicon cell channel layer is substantially halogen-free.
4 . The apparatus of claim 1 , wherein the AWGHM of the polysilicon cell channel layer is greater than 40 nanometers.
5 . The apparatus of claim 1 , wherein the AWGHM of the polysilicon cell channel layer is greater than 50 nanometers.
6 . The apparatus of claim 1 , wherein the AWGHM of the polysilicon cell channel layer is greater than 60 nanometers.
7 . The apparatus of claim 1 , further comprising:
a tunnel oxide layer adjacent to the polysilicon cell channel layer, wherein the polysilicon cell channel layer is substantially chlorine-free at an interface between the polysilicon cell channel layer and the tunnel oxide layer.
8 . A memory device, comprising:
a controller; and
NAND memory coupled to the controller, the NAND memory comprising:
an array of vertical NAND strings, wherein a polysilicon vertical cell channel of the array includes a plurality of NAND cells arranged along the polysilicon vertical cell channel with a tunnel oxide layer disposed between the plurality of NAND cells and the polysilicon vertical cell channel, and wherein the polysilicon vertical cell channel comprises less than E17 halogen atoms per cubic centimeter, wherein a thickness of the polysilicon vertical cell channel is less than or equal to 25 nanometers, and wherein an area-weighted grain height mean (AWGHM) of the polysilicon vertical cell channel is greater than 30 nanometers.
9 . The memory device of claim 8 , wherein the polysilicon vertical cell channel comprises less than E16 halogen atoms per cubic centimeter.
10 . The memory device of claim 8 , wherein the polysilicon vertical cell channel is substantially halogen-free.
11 . The memory device of claim 8 , wherein the AWGHM of the polysilicon vertical cell channel is greater than 50 nanometers.
12 . The memory device of claim 8 , wherein the AWGHM at a middle portion of the polysilicon vertical cell channel is greater than 60 nanometers.
13 . The memory device of claim 8 , wherein the polysilicon vertical cell channel is substantially chlorine-free at an interface between the polysilicon vertical cell channel and the tunnel oxide layer.
14 . The memory device of claim 8 , wherein the NAND memory comprises three-dimensional NAND memory.
15 . A system, comprising:
a processor; and
a three-dimensional (3D) NAND memory device coupled to the processor, the 3D NAND memory device comprising:
3D NAND media comprising an array of vertical NAND strings, wherein a polysilicon vertical cell channel of the array includes a plurality of NAND cells arranged along the polysilicon vertical cell channel with a dielectric material disposed between the plurality of NAND cells and the polysilicon vertical cell channel, and wherein the polysilicon vertical cell channel comprises less than E17 halogen atoms per cubic centimeter, wherein a thickness of the polysilicon vertical cell channel is less than or equal to 25 nanometers, and wherein an area-weighted grain height mean (AWGHM) of the polysilicon vertical cell channel is greater than 30 nanometers.
16 . The system of claim 15 , wherein the polysilicon vertical cell channel comprises less than E16 halogen atoms per cubic centimeter.
17 . The system of claim 15 , wherein the polysilicon vertical cell channel is substantially halogen-free.
18 . The system of claim 15 , wherein the AWGHM of the polysilicon vertical cell channel is greater than 45 nanometers.
19 . The system of claim 15 , wherein the AWGHM at a middle portion of the polysilicon vertical cell channel is greater than 60 nanometers.
20 . The system of claim 15 , wherein the polysilicon vertical cell channel is substantially chlorine-free at an interface between the polysilicon vertical cell channel and the dielectric material.