Metal hybrid charge storage structure for memory
Systems, apparatuses and methods may provide for memory cell technology comprising a control gate, a conductive channel, and a charge storage structure coupled to the control gate and the conductive channel, wherein the charge storage structure includes a polysilicon layer and a metal layer. In one example, the metal layer includes titanium nitride or other high effective work function metal.
1 . A memory cell, comprising:
a control gate;
a conductive channel; and
a charge storage structure coupled to the control gate and the conductive channel, wherein the charge storage structure includes a polysilicon layer and a metal layer, wherein the polysilicon layer is positioned between the metal layer and the conductive channel, the charge storage structure is coupled to the control gate via two dielectric layers, a first dielectric layer of the two dielectric layers contacts the polysilicon layer of the charge storage structure, and a second dielectric layer of the two dielectric layers directly contacts both the polysilicon layer and the metal layer of the charge storage structure via a plurality of sides of each of the polysilicon layer and the metal layer.
2 . The memory cell of claim 1 , wherein the metal layer includes titanium nitride.
3 . The memory cell of claim 1 , wherein the charge storage structure is coupled to the control gate via four dielectric layers.
4 . The memory cell of claim 3 , wherein the four dielectric layers include interpoly dielectric layers.
5 . The memory cell of claim 1 , wherein the first dielectric layer contacts the polysilicon layer via a first surface of the polysilicon layer, and a portion of the first surface is recessed towards the metal layer.
6 . The memory cell of claim 1 , wherein the memory cell is a penta level cell.
7 . A computing system, comprising:
a motherboard;
a processor coupled to the motherboard; and
a memory device coupled to the motherboard, wherein the memory device includes a plurality of memory cells, and wherein one or more of the memory cells includes:
a control gate,
a conductive channel, and
a charge storage structure coupled to the control gate and the conductive channel, wherein the charge storage structure includes a polysilicon layer and a metal layer, and wherein the polysilicon layer is positioned between the metal layer and the conductive channel, the charge storage structure is coupled to the control gate via two dielectric layers, a first dielectric layer of the two dielectric layers contacts the polysilicon layer of the charge storage structure, and a second dielectric layer of the two dielectric layers directly contacts both the polysilicon layer and the metal layer of the charge storage structure via a plurality of sides of each of the polysilicon layer and the metal layer.
8 . The computing system of claim 7 , wherein the metal layer includes titanium nitride.
9 . The computing system of claim 7 , wherein the charge storage structure is coupled to the control gate via four dielectric layers.
10 . The computing system of claim 9 , wherein the four dielectric layers include interpoly dielectric layers.
11 . The computing system of claim 7 , wherein the two dielectric layers include an interpoly dielectric layer.
12 . The computing system of claim 7 , wherein each of the plurality of memory cells is a penta level cell.
13 . A method of fabricating a memory cell, the method comprising:
coupling a charge storage structure to a control gate, wherein the charge storage structure includes a polysilicon layer and a metal layer; and
coupling a conductive channel to the charge storage structure, wherein the polysilicon layer is positioned between the metal layer and the conductive channel, the charge storage structure is coupled to the control gate via two dielectric layers, a first dielectric layer of the two dielectric layers contacts the polysilicon layer of the charge storage structure, and a second dielectric layer of the two dielectric layers directly contacts both the polysilicon layer and the metal layer of the charge storage structure via a plurality of sides of each of the polysilicon layer and the metal layer.
14 . The method of claim 13 , wherein the metal layer includes titanium nitride.
15 . The method of claim 13 , wherein the charge storage structure is coupled to the control gate via four dielectric layers.
16 . The method of claim 15 , wherein the four dielectric layers include interpoly dielectric layers.
17 . The method of claim 13 , wherein the two dielectric layers include an interpoly dielectric layer.
18 . The memory cell of claim 1 , wherein the plurality of sides of each of the polysilicon layer and the metal layer includes a bottom side of the metal layer adjacent to the control gate and at least one peripheral side of the metal layer connected to the bottom side of the metal layer.
19 . The memory cell of claim 1 , wherein the first dielectric layer wraps around the charge storage structure and the second dielectric layer.
20 . The memory cell of claim 1 , wherein the first dielectric layer includes a single type of dielectric material filling a gap between the control gate and the second dielectric layer.