ORGANIC SPACER FOR INTEGRATED CIRCUITS
Embodiments of the present disclosure are directed to organic spacers for integrated circuits. Among other things, the organic spacers of the embodiments of the present disclosure help provide a cost-efficient and effective solution to address issues such as coefficient of thermal expansion (CTE) mismatches, dynamic warpage, and solder joint reliability (SJR). Other embodiments may be described and claimed.
1 - 20 . (canceled)
21 . An apparatus comprising:
a semiconductor substrate;
a silicon die; and
a spacer disposed between the silicon die and the semiconductor substrate, wherein the spacer comprises an organic compound, and wherein the spacer is provided to reduce a coefficient of thermal expansion (CTE) mismatch between the semiconductor substrate and silicon die.
22 . The apparatus of claim 21 , wherein the organic compound comprises an epoxy mold compound (EMC) or an organic solder mask material.
23 . The apparatus of claim 21 , wherein the silicon die includes a film layer, and wherein the film layer is in contact with the spacer.
24 . The apparatus of claim 21 , wherein the silicon die is a first silicon die, and the apparatus further comprises a second silicon die in contact with the semiconductor substrate.
25 . The apparatus of claim 24 , wherein the second silicon die is free from contact with the first silicon die or the EMC spacer.
26 . The apparatus of claim 24 , wherein the apparatus further comprises a third silicon die disposed between first silicon die and the second silicon die.
27 . The apparatus of claim 24 , wherein each respective silicon die includes a respective film layer.
28 . The apparatus of claim 21 , wherein the silicon die is a first silicon die, wherein a first side of the first silicon die is in contact with the spacer, and wherein a second side of the first silicon die is in contact with a second silicon die.
29 . The apparatus of claim 28 , wherein the first silicon die includes a first film layer on its first side contacting the spacer, and wherein the second silicon die includes a second film layer in contact with second side of the first silicon die.
30 . The apparatus of claim 21 , wherein the silicon die is a first silicon die and the spacer is a first spacer, and wherein the apparatus further comprises:
a second silicon die; and
a second spacer adjacent to the first spacer, the second spacer disposed between the substrate and the second silicon die.
31 . A method comprising:
molding a wafer comprising an organic spacer on a glass carrier, the organic spacer having a target type and a target thickness; and
cutting the wafer to provide one or more organic spacer bricks having the target thickness, wherein the one or more organic spacer bricks are to be disposed on a substrate of an electronic device to reduce a coefficient of thermal expansion (CTE) mismatch between the substrate and a silicon die of the electronic device based on the target type.
32 . The method of claim 31 , further comprising attaching the one or more organic spacer bricks to the substrate of the electronic device to provide a spacer layer between the substrate and the silicon die of the electronic device, wherein the silicon die is disposed or to be disposed on the substrate.
33 . The method of claim 31 , wherein the organic spacer has a target type that comprises an epoxy mold compound (EMC) or an organic solder mask material.
34 . The method of claim 31 , wherein cutting the wafer includes providing the one or more spacer bricks with a target size, the target size including the target thickness, a target length, and a target width.
35 . The method of claim 31 , wherein the silicon die is a first silicon die, and the electronic device further comprises a second silicon die in contact with the substrate.
36 . The method of claim 35 , wherein the second silicon die is free from contact with the first silicon die or the organic spacer.
37 . A computing device comprising:
a circuit board; and
a package die coupled with the circuit board, the package die including:
a semiconductor substrate;
a silicon die; and
a spacer disposed between the silicon die and the semiconductor substrate wherein the spacer comprises an organic compound, and wherein the spacer is provided to reduce a coefficient of thermal expansion (CTE) mismatch between the semiconductor substrate and silicon die.
38 . The computing device of claim 37 , wherein the organic compound comprises an epoxy mold compound (EMC) or an organic solder mask material.
39 . The computing device of claim 37 , wherein the silicon die includes a film layer, and wherein the film layer is in contact with the spacer.
40 . The computing device of claim 37 , wherein the silicon die is a first silicon die, and the package die further comprises a second silicon die in contact with the semiconductor substrate.