IP Library Patent Application 18249635
Patent Application
App. No. 18/249,635

MEMORY DEVICES WITH GRADIENT-DOPED CONTROL GATE MATERIAL

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Quick Facts
Patent No.
US None
App. No.
18/249,635
Abstract

Disclosed herein are memory devices with gradient-doped control gate material, as well as related methods and devices. In some embodiments, a memory device may include a first isolation material, a second isolation material, and a control gate material between the first isolation material and the second isolation material along an axis. The control gate material may include a dopant having a non-uniform concentration along the axis.

Claims (34)

1 . A memory device, comprising:

a first isolation material;

a second isolation material; and

a control gate material between the first isolation material and the second isolation material along an axis, wherein the control gate material includes a dopant having a non-uniform concentration along the axis.

2 . The memory device of claim 1 , wherein the control gate material includes polysilicon.

3 . The memory device of claim 1 , wherein the dopant includes phosphorous.

4 . The memory device of claim 1 , wherein the first isolation material includes oxygen.

5 . The memory device of claim 1 , wherein the dopant has a concentration that is greatest at a location proximate to a center of the control gate material along the axis.

6 . The memory device of claim 1 , wherein the dopant has a concentration that is least at a location proximate to a center of the control gate material along the axis.

7 . The memory device of claim 1 , wherein the dopant has a concentration that increases from the first isolation material towards the second isolation material.

8 . A memory device, comprising:

an isolation material; and

a control gate material in contact with the isolation material, wherein the control gate material is recessed relative to the isolation material in a first direction, the control gate material includes a dopant having a non-uniform concentration in a second direction perpendicular to the first direction.

9 . The memory device of claim 8 , further comprising:

a dielectric material in contact with the isolation material and in contact with the control gate material, wherein the dielectric material has a material composition that is different from a material composition of the isolation material.

10 . The memory device of claim 9 , further comprising:

a floating gate material, wherein the dielectric material is between the floating gate material and the control gate material.

11 . The memory device of claim 8 , further comprising:

a tunnel dielectric material proximate to a face of the isolation material.

12 . The memory device of claim 11 , further comprising:

a cell pillar material, wherein the tunnel dielectric material is between the cell pillar material and the isolation material.

13 . The memory device of claim 8 , wherein the dopant has a concentration that increases towards the isolation material.

14 . The memory device of claim 8 , wherein the dopant has a concentration that decreases towards the isolation material.

15 . A memory device, comprising:

an oxide-polysilicon-oxide stack having a polysilicon layer between two oxide layers, wherein the polysilicon layer is recessed relative to the oxide layers;

wherein the polysilicon layer has a non-uniform concentration of phosphorous therein.

16 . The memory device of claim 15 , wherein the polysilicon layer has a phosphorous concentration that is greatest proximate to a location in the polysilicon layer equidistant from the oxide layers.

17 . The memory device of claim 15 , further comprising:

a dielectric material between the oxide layers, wherein the dielectric material has a material composition that is different from a material composition of the oxide layers.

18 . The memory device of claim 17 , wherein the dielectric material has a C-shaped cross-section.

19 . The memory device of claim 17 , further comprising:

a polysilicon region between the oxide layers, wherein the dielectric material is between the polysilicon layer and the polysilicon region.

20 . The memory device of claim 15 , further comprising:

a tunnel dielectric material proximate to side faces of the oxide layers.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 2, 2024
From: INTEL CORPORATION
To: INTEL NDTM US LLC
Reel/Frame 067305/0491 →