Dynamic detection and dynamic adjustment of sub-threshold swing in a memory cell sensing circuit
For a nonvolatile (NV) storage media such as NAND media that is written by a program and program verify operation, the system can determine an expected number of SSPC (selective slow programming convergence) cells for a page of cells for specific conditions of the page. The system can perform program verify with a first wordline (WL) select voltage for SSPC cell detection for a first write of the page to detect the expected number of SSPC cells. Based on the determined expected number of SSPC cells, the system can set a boost voltage to capture an expected number of SSPC cells during the program verify operation. The system performs program verify for subsequent writes to the page with a higher WL select voltage, to perform program verify for standard cells and then SSPC program verify with the boost voltage determined from the first write.
1. An apparatus comprising:
a nonvolatile (NV) storage media to be written by an operation to program a cell and then perform program verify of the cell, the NV storage media to be written as a page of cells; and
a controller to perform program verify with a first wordline (WL) select voltage for SSPC (selective slow programming convergence) cell detection for a first write of the page of cells to detect an expected number of SSPC cells, compute a boost voltage to capture approximately the expected number of SSPC cells, and perform program verify with a second WL select voltage higher than the first WL select voltage for subsequent writes of the page of cells, to perform program verify for standard cells and then SSPC program verify with the boost voltage computed to capture approximately the expected number of SSPC cells.
2. The apparatus of claim 1 , wherein the first WL select voltage comprises a voltage approximately one-half a program step voltage lower than a WL program voltage.
3. The apparatus of claim 1 , further comprising:
a boost circuit to generate the boost voltage, including to generate a sequence of SSPC boost voltages to determine the boost voltage to capture approximately the expected number of SSPC cells.
4. The apparatus of claim 3 , wherein the sequence of SSPC boost voltages comprises a linear search sequence.
5. The apparatus of claim 3 , wherein the sequence of SSPC boost voltages comprises a binary search sequence.
6. The apparatus of claim 1 , wherein the controller is to compute the boost voltage to capture approximately the expected number of SSPC cells based on the expected number of SSPC cells for a changed condition for the NV storage media.
7. The apparatus of claim 6 , wherein the changed condition comprises a temperature change.
8. The apparatus of claim 6 , wherein the changed condition comprises a different wordline position.
9. The apparatus of claim 6 , wherein the changed condition comprises a change in cycling count.
10. The apparatus of claim 1 , wherein the cell comprises a 3D (three-dimensional) NAND memory cell.
11. A system comprising:
a processor;
a solid state drive (SSD) coupled to the processor, the SSD including
a nonvolatile (NV) storage media to be written by an operation to program a cell and then perform program verify of the cell, the NV storage media to be written as a page of cells; and
a controller to perform program verify with a first wordline (WL) select voltage for SSPC (selective slow programming convergence) cell detection for a first write of the page of cells to detect an expected number of SSPC cells, compute a boost voltage to capture approximately the expected number of SSPC cells, and perform program verify with a second WL select voltage higher than the first WL select voltage for subsequent writes of the page of cells, to perform program verify for standard cells and then SSPC program verify with the boost voltage computed to capture approximately the expected number of SSPC cells.
12. The system of claim 11 , wherein the first WL select voltage comprises a voltage approximately one-half a program step voltage lower than a WL program voltage.
13. The system of claim 11 , the SSD further including:
a boost circuit to generate the boost voltage, including to generate a sequence of SSPC boost voltages to determine the boost voltage to capture approximately the expected number of SSPC cells.
14. The system of claim 13 , wherein the sequence of SSPC boost voltages comprises a linear search sequence.
15. The system of claim 13 , wherein the sequence of SSPC boost voltages comprises a binary search sequence.
16. The system of claim 11 , wherein the controller is to compute the boost voltage to capture approximately the expected number of SSPC cells based on the expected number of SSPC cells for a temperature change, a different wordline position, or a change in cycling count for the NV storage media.
17. The system of claim 11 , wherein the cell comprises a 3D (three-dimensional) NAND memory cell.
18. A method for program verify of a cell, comprising:
performing program verify with a first wordline (WL) select voltage for SSPC (selective slow programming convergence) cell detection for a first write of a page of cells of a nonvolatile (NV) storage media, to detect an expected number of SSPC cells; and
computing a boost voltage to capture approximately the expected number of SSPC cells; and
performing program verify with a second WL select voltage higher than the first WL select voltage for subsequent writes of the page of cells, to perform program verify for standard cells and then SSPC program verify with the boost voltage computed to capture approximately the expected number of SSPC cells.
19. The method of claim 18 , further comprising:
generating the boost voltage, including generating a sequence of SSPC boost voltages to determine the boost voltage to capture approximately the expected number of SSPC cells.
20. The method of claim 18 , further comprising:
computing the boost voltage to capture approximately the expected number of SSPC cells based on the expected number of SSPC cells for a temperature change, a different wordline position, or a change in cycling count for the NV storage media.
21. The method of claim 20 , wherein computing the boost voltage comprises performing a linear search sequence or performing a binary search sequence.