Parallel staircase 3D NAND
Systems, apparatuses, and methods may provide for technology that arranges stair wells for memory devices. The memory device includes a memory array and a memory block coupled to the memory array. The memory block includes a first through array via area and a first staircase area coupled to a plurality of decks. The first staircase area includes a first stair well and a second stair well located contiguous to the first stair well.
1 . A memory device comprising:
a memory array including two memory portions separated by a separation area; and
two memory blocks disposed in the separation area, the two memory blocks coupled between the two memory portions, the two memory blocks further including:
a first memory block coupled to the memory array, the first memory block comprising:
a first through array via area; and
a first staircase area coupled to a plurality of decks, wherein the first staircase area comprises a first stair well and a second stair well located contiguous to the first stair well; and
a second memory block coupled to the memory array, the second memory block including a second staircase area having at least two contiguous stair wells.
2 . The memory device of claim 1 , wherein the first staircase area comprises a third stair well located contiguous to the first and second stair wells.
3 . The memory device of claim 1 , wherein the first stair well is coupled exclusively to a first one of the plurality of decks, and wherein the second stair well is coupled exclusively to a second one of the plurality of decks, wherein the second stair well is different than the first stair well and the second one of the plurality of decks is different than the first one of the plurality of decks.
4 . The memory device of claim 3 , the second memory block further comprising a second through array via area, wherein the second staircase area is coupled to the plurality of decks.
5 . The memory device of claim 4 , wherein the first and second staircase areas and the first and second through array via areas form a sandwich structure with the first and second staircase areas located on an outside of the sandwich structure and the first and second through array via areas positioned adjacent one another on an inside of the sandwich structure.
6 . The memory device of claim 4 , wherein the first and second staircase areas and the first and second through array via areas extend parallel to one another and perpendicular to the memory array.
7 . The memory device of claim 1 , wherein the first through array via area comprises a plurality of string driver contacts, wherein the first staircase area comprises a plurality of word line contacts, and wherein a plurality of metal routers individually connect the plurality of word line contacts to the plurality of string driver contacts, and wherein the plurality of metal routers extend parallel to the memory array.
8 . A system comprising:
a memory controller; and
a multi-deck non-volatile memory structure coupled to the memory controller, the multi-deck non-volatile memory structure comprising a plurality of decks, multi-deck non-volatile memory structure comprising:
a memory array including two memory portions separated by a separation area; and
two memory blocks disposed in the separation area, the two memory blocks coupled between the two memory portions, the two memory blocks further including:
a first memory block coupled to the memory array, the first memory block comprising:
a first through array via area; and
a first staircase area coupled to the plurality of decks, wherein the first staircase area comprises a first stair well and a second stair well located contiguous to the first stair well; and
a second memory block coupled to the memory array, the second memory block including a second staircase area having at least two contiguous stair wells.
9 . The system of claim 8 , wherein the first staircase area comprises a third stair well located contiguous to the first and second stair wells.
10 . The system of claim 8 , wherein the first stair well is coupled exclusively to a first one of the plurality of decks, and wherein the second stair well is coupled exclusively to a second one of the plurality of decks, wherein the second stair well is different than the first stair well and the second one of the plurality of decks is different than the first one of the plurality of decks.
11 . The system of claim 10 , the second memory block further comprising a second through array via area, wherein the second staircase area is coupled to the plurality of decks.
12 . The system of claim 11 , wherein the first and second staircase areas and the first and second through array via areas form a sandwich structure with the first and second staircase areas located on an outside of the sandwich structure and the first and second through array via areas positioned adjacent one another on an inside of the sandwich structure.
13 . The system of claim 11 , wherein the first and second staircase areas and the first and second through array via areas extend parallel to one another and perpendicular to the memory array.
14 . The system of claim 8 , wherein the first through array via area comprises a plurality of string driver contacts, wherein the first staircase area comprises a plurality of word line contacts, and wherein a plurality of metal routers individually connect the plurality of word line contacts to the plurality of string driver contacts, and wherein the plurality of metal routers extend parallel to the memory array.
15 . A method comprising:
forming a memory array, the memory array including two memory portions separated by a separation area; and
forming two memory blocks disposed in the separation area, the two memory blocks coupled to the memory array and between the two memory portions, wherein forming the two memory blocks further includes:
forming a first memory block, the first memory block comprising:
a first through array via area; and
a first staircase area coupled to a plurality of decks, wherein the first staircase area comprises a first stair well and a second stair well located contiguous to the first stair well; and
forming a second memory block coupled to the memory array, the second memory block including a second staircase area having at least two contiguous stair wells.
16 . The method of claim 15 , wherein the first staircase area comprises a third stair well located contiguous to the first and second stair wells.
17 . The method of claim 15 , wherein the first stair well is coupled exclusively to a first one of the plurality of decks, and wherein the second stair well is coupled exclusively to a second one of the plurality of decks, wherein the second stair well is different than the first stair well and the second one of the plurality of decks is different than the first one of the plurality of decks.
18 . The method of claim 17 , wherein the second memory block further comprises a second through array via area, wherein the second staircase area is coupled to the plurality of decks.
19 . The method of claim 18 , wherein the first and second staircase areas and the first and second through array via areas form a sandwich structure with the first and second staircase areas located on an outside of the sandwich structure and the first and second through array via areas positioned adjacent one another on an inside of the sandwich structure, and wherein the first and second staircase areas and the first and second through array via areas extend parallel to one another and perpendicular to the memory array.
20 . The method of claim 15 , wherein the first through array via area comprises a plurality of string driver contacts, wherein the first staircase area comprises a plurality of word line contacts, and wherein a plurality of metal routers individually connect the plurality of word line contacts to the plurality of string driver contacts, and wherein the plurality of metal routers extend parallel to the memory array.