Vertical memory device and method

1. A memory cell, comprising:

a substrate;

a body extending vertically from said substrate;

a first gate comprising a vertical member and a horizontal member, wherein said first gate is disposed laterally from said body; and

a second gate comprising a vertical member and a horizontal member, wherein said second gate is disposed laterally from said first gate;

wherein said horizontal member of said first gate overlaps said horizontal member of said second gate.

2. The memory cell of claim 1 , wherein said first and second gates comprise polysilicon.

3. The memory cell of claim 1 , further comprising a first dielectric formed between said first gate and said body.

4. The memory cell of claim 3 , wherein said first dielectric comprises a vertical portion having a first thickness adjacent to said body and a horizontal portion having a second thickness adjacent to said substrate, wherein said second thickness is greater than said first thickness.

5. The memory cell of claim 4 , wherein said first dielectric comprises an oxide.

6. The memory cell of claim 3 , further comprising a second dielectric between said first and second gates.

7. The memory cell of claim 6 , wherein said second dielectric comprises an oxide-nitride-oxide.

8. The memory cell of claim 1 , wherein a capacitive coupling ratio between said first and second gates is between 0.3 and 0.6.

9. A memory array, comprising:

multiple memory cells, wherein each of said multiple memory cells comprises a substrate; a body extending vertically from said substrate, a source, and a drain; a first gate comprising a vertical member and a horizontal member, wherein said first gate is disposed laterally from said body; and a second gate comprising a vertical member and a horizontal member, wherein said second gate is disposed laterally from said first gate;

wherein said horizontal member of said first gate overlaps said horizontal member of said second gate;

multiple gate lines interconnecting said second gates of each of said multiple memory cells;

multiple drain lines interconnecting said drains of each of said multiple memory cells; and

multiple source lines interconnecting said sources of each of said multiple memory cells.

10. The memory array of claim 9 , wherein said first and second gates comprise polysilicon.

11. The memory array of claim 9 , further comprising a first dielectric formed between said first gate and said body.

12. The memory array of claim 11 , wherein said first dielectric comprises a vertical portion having a first thickness adjacent to said body and a horizontal portion having a second thickness adjacent to said substrate, wherein said second thickness is greater than said first thickness.

13. The memory array of claim 9 , wherein a capacitive coupling ratio between said first and second gates is between 0.3 and 0.6.

14. An apparatus, comprising:

a random access memory comprising multiple memory cells;

wherein each of said multiple memory cells comprises:

a substrate;

a body extending vertically from said substrate;

a first gate comprising a vertical member and a horizontal member, wherein said first gate is disposed laterally from said body; and

a second gate comprising a vertical member and a horizontal member, wherein said second gate is disposed laterally from said first gate;

wherein said horizontal member of said first gate overlaps said horizontal member of said second gate.

15. The apparatus of claim 14 , wherein the random access memory is a dynamic random access memory.

16. The apparatus of claim 14 , wherein the random access memory is a static random access memory.

17. The apparatus of claim 14 , wherein the random access memory is a synchronous random access memory.